b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
52 lines
2.2 KiB
LLVM
52 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx,+fma,+f16c,+avx512f -stop-after finalize-isel -o - %s | FileCheck %s
|
|
; This test ensures that the MXCSR is implicitly used by MMX FP instructions.
|
|
|
|
define <1 x i64> @mxcsr_mmx(<4 x float> %a0) {
|
|
; CHECK: MMX_CVTPS2PIrr %{{[0-9]}}, implicit $mxcsr
|
|
; CHECK: MMX_CVTPI2PSrr %{{[0-9]}}, killed %{{[0-9]}}, implicit $mxcsr
|
|
; CHECK: MMX_CVTTPS2PIrr killed %{{[0-9]}}, implicit $mxcsr
|
|
; CHECK: MMX_CVTPI2PDrr killed %{{[0-9]$}}
|
|
; CHECK: MMX_CVTPD2PIrr killed %{{[0-9]}}, implicit $mxcsr
|
|
%1 = call <1 x i64> @llvm.x86.sse.cvtps2pi(<4 x float> %a0)
|
|
%2 = call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a0, <1 x i64> %1)
|
|
%3 = call <1 x i64> @llvm.x86.sse.cvttps2pi(<4 x float> %2)
|
|
%4 = call <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64> %3)
|
|
%5 = call <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double> %4)
|
|
ret <1 x i64> %5
|
|
}
|
|
|
|
define half @mxcsr_f16c(float %a) {
|
|
; CHECK: VCVTPS2PH{{.*}}mxcsr
|
|
%res = fptrunc float %a to half
|
|
ret half %res
|
|
}
|
|
|
|
define <4 x float> @mxcsr_fma_ss(<4 x float> %a, <4 x float> %b) {
|
|
; CHECK: VFMADD{{.*}}mxcsr
|
|
%res = call <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float> %b, <4 x float> %a, <4 x float>
|
|
%a)
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
define <4 x float> @mxcsr_fma_ps(<4 x float> %a, <4 x float> %b) {
|
|
; CHECK: VFMADD{{.*}}mxcsr
|
|
%res = call <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %b, <4 x float> %a, <4 x float>
|
|
%a)
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
define <8 x double> @mxcsr_fma_sae(<8 x double> %a, <8 x double> %b, <8 x double> %c) {
|
|
; CHECK: VFMADD{{.*}}mxcsr
|
|
%res = call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 -1, i32 10)
|
|
ret <8 x double> %res
|
|
}
|
|
|
|
declare <1 x i64> @llvm.x86.sse.cvtps2pi(<4 x float>)
|
|
declare<4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>)
|
|
declare <1 x i64> @llvm.x86.sse.cvttps2pi(<4 x float>)
|
|
declare <2 x double> @llvm.x86.sse.cvtpi2pd(<1 x i64>)
|
|
declare <1 x i64> @llvm.x86.sse.cvtpd2pi(<2 x double>)
|
|
declare <4 x float> @llvm.x86.fma.vfmadd.ss(<4 x float>, <4 x float>, <4 x float>)
|
|
declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float>, <4 x float>, <4 x float>)
|
|
declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
|