b651fdff79
matchRotateSub is given shift amounts that will already have stripped any/zero-extend nodes from - so make sure those values are wide enough to take a mask.
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
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; Ensure that the (pre-extended) shift amount type is wide enough to take any mask.
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define void @PR56859() {
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; X86-LABEL: PR56859:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl (%eax), %ecx
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; X86-NEXT: testl %ecx, %ecx
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; X86-NEXT: setne %al
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; X86-NEXT: movl $1, %edx
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; X86-NEXT: # kill: def $cl killed $cl killed $ecx
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; X86-NEXT: shrl %cl, %edx
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; X86-NEXT: btsl %eax, %edx
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; X86-NEXT: movl %edx, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: PR56859:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl (%rax), %ecx
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; X64-NEXT: testl %ecx, %ecx
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; X64-NEXT: setne %al
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; X64-NEXT: movl $1, %edx
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shrl %cl, %edx
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; X64-NEXT: btsl %eax, %edx
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; X64-NEXT: movl %edx, (%rax)
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; X64-NEXT: retq
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entry:
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%0 = load i32, ptr undef, align 4
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%tobool = icmp ne i32 %0, 0
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%lor.ext = zext i1 %tobool to i32
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%shr = lshr i32 1, %0
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%shl = shl i32 1, %lor.ext
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%or = or i32 %shl, %shr
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store i32 %or, ptr undef, align 4
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ret void
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}
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