cf6cd1fd67
This doesn't match uops.info yet - but it matches the existing vpscatterdq/vscatterqpd entries like uops.info says it should Reapplied with codegen fix for scatter-schedule.ll Fixes #105675
23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=skx < %s | FileCheck %s
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target triple = "x86_64-unknown-linux-gnu"
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; This test checks the order of scatter operations after split.
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; The right order is "from LSB to MSB", otherwise the semantic is broken.
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define void @test(i64 %x272, <16 x ptr> %x335, <16 x i32> %x270) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: kxnorw %k0, %k0, %k1
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; CHECK-NEXT: vpscatterqd %ymm2, (,%zmm0) {%k1}
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; CHECK-NEXT: kxnorw %k0, %k0, %k1
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; CHECK-NEXT: vextracti64x4 $1, %zmm2, %ymm0
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; CHECK-NEXT: vpscatterqd %ymm0, (,%zmm1) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %x270, <16 x ptr> %x335, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
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ret void
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}
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declare void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> , <16 x ptr> , i32, <16 x i1> )
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