b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
117 lines
3.4 KiB
LLVM
117 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X64
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; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X86
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; From source: clang -02
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;__m64 test47(int a)
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;{
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; __m64 x = (a)? (__m64)(7): (__m64)(0);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test47(i64 %arg) {
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;
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; X64-LABEL: test47:
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; X64: # %bb.0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: movl $7, %ecx
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; X64-NEXT: cmovneq %rax, %rcx
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; X64-NEXT: movq %rcx, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test47:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .cfi_offset %ebp, -8
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: .cfi_def_cfa_register %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $16, %esp
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; X86-NEXT: movl 8(%ebp), %eax
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; X86-NEXT: orl 12(%ebp), %eax
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; X86-NEXT: movl $7, %eax
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; X86-NEXT: je .LBB0_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: .LBB0_2:
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; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; X86-NEXT: psllw %mm0, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: .cfi_def_cfa %esp, 4
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; X86-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%slct = select i1 %cond, <1 x i64> bitcast (i64 7 to <1 x i64>), <1 x i64> bitcast (i64 0 to <1 x i64>)
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%psll = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> %slct, <1 x i64> %slct)
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%retc = bitcast <1 x i64> %psll to i64
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ret i64 %retc
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}
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; From source: clang -O2
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;__m64 test49(int a, long long n, long long m)
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;{
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; __m64 x = (a)? (__m64)(n): (__m64)(m);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test49(i64 %arg, i64 %x, i64 %y) {
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;
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; X64-LABEL: test49:
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; X64: # %bb.0:
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: cmovneq %rdx, %rsi
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; X64-NEXT: movq %rsi, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test49:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .cfi_offset %ebp, -8
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: .cfi_def_cfa_register %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl 8(%ebp), %eax
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; X86-NEXT: orl 12(%ebp), %eax
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; X86-NEXT: je .LBB1_1
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; X86-NEXT: # %bb.2:
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; X86-NEXT: leal 24(%ebp), %eax
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; X86-NEXT: jmp .LBB1_3
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; X86-NEXT: .LBB1_1:
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; X86-NEXT: leal 16(%ebp), %eax
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; X86-NEXT: .LBB1_3:
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; X86-NEXT: movq (%eax), %mm0
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; X86-NEXT: psllw %mm0, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: .cfi_def_cfa %esp, 4
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; X86-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%xmmx = bitcast i64 %x to <1 x i64>
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%ymmx = bitcast i64 %y to <1 x i64>
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%slct = select i1 %cond, <1 x i64> %xmmx, <1 x i64> %ymmx
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%psll = tail call <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64> %slct, <1 x i64> %slct)
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%retc = bitcast <1 x i64> %psll to i64
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ret i64 %retc
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}
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declare <1 x i64> @llvm.x86.mmx.psll.w(<1 x i64>, <1 x i64>)
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