0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
342 lines
9.7 KiB
LLVM
342 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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; If positive...
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define i32 @zext_ifpos(i32 %x) {
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; CHECK-LABEL: zext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_zext_ifpos(i32 %x) {
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; CHECK-LABEL: add_zext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_zext_ifpos_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]
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; CHECK-NEXT: psubd %xmm0, %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = zext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define <4 x i32> @add_zext_ifpos_vec_nonsplat(<4 x i32> %x) {
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; CHECK-LABEL: add_zext_ifpos_vec_nonsplat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,43,44,45]
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; CHECK-NEXT: psubd %xmm0, %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = zext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_tval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifpos(i32 %x) {
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; CHECK-LABEL: sext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_sext_ifpos(i32 %x) {
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; CHECK-LABEL: add_sext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $31, %edi
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; CHECK-NEXT: leal 41(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_sext_ifpos_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = sext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define <4 x i32> @add_sext_ifpos_vec_nonsplat(<4 x i32> %x) {
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; CHECK-LABEL: add_sext_ifpos_vec_nonsplat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = sext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_fval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $31, %edi
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; CHECK-NEXT: leal 41(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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; If negative...
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define i32 @zext_ifneg(i32 %x) {
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; CHECK-LABEL: zext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_zext_ifneg(i32 %x) {
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; CHECK-LABEL: add_zext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $31, %edi
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; CHECK-NEXT: leal 41(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define i32 @sel_ifneg_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_tval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $31, %edi
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; CHECK-NEXT: leal 41(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifneg(i32 %x) {
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; CHECK-LABEL: sext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%r = sext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_sext_ifneg(i32 %x) {
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; CHECK-LABEL: add_sext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define i32 @sel_ifneg_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_fval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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define i32 @add_lshr_not(i32 %x) {
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; CHECK-LABEL: add_lshr_not:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = add i32 %sh, 41
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ret i32 %r
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}
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define <4 x i32> @add_lshr_not_vec_nonsplat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_nonsplat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = add <4 x i32> %e, <i32 42, i32 43, i32 44, i32 45>
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ret <4 x i32> %r
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}
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define i32 @sub_lshr_not(i32 %x) {
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; CHECK-LABEL: sub_lshr_not:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $31, %edi
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; CHECK-NEXT: leal 42(%rdi), %eax
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; CHECK-NEXT: retq
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrld $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
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ret <4 x i32> %r
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}
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define <4 x i32> @sub_lshr_not_vec_nonsplat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_nonsplat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrld $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %e
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ret <4 x i32> %r
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}
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define i32 @sub_lshr(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal (%rdi,%rsi), %eax
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; CHECK-NEXT: retq
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%sh = lshr i32 %x, 31
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%r = sub i32 %y, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: sub_lshr_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: paddd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> %y, %sh
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ret <4 x i32> %r
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}
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define i32 @sub_const_op_lshr(i32 %x) {
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; CHECK-LABEL: sub_const_op_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: sarl $31, %edi
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; CHECK-NEXT: leal 43(%rdi), %eax
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; CHECK-NEXT: retq
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%sh = lshr i32 %x, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_const_op_lshr_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_const_op_lshr_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
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ret <4 x i32> %r
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}
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define <4 x i32> @sub_const_op_lshr_vec_nonsplat(<4 x i32> %x) {
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; CHECK-LABEL: sub_const_op_lshr_vec_nonsplat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 43, i32 44, i32 45>, %sh
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ret <4 x i32> %r
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}
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