cbdccb30c2
If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed. The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch. Differential Revision: https://reviews.llvm.org/D156491
81 lines
2.9 KiB
LLVM
81 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; %ptr has a hint to %rdi in entry block, it also has a interference with %rdi
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; in block if.then. It should be split in cold block if.then.
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; Similarly %p2, %p3, %p4, %p5 and %p6 should also be split in cold block
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; if.then.
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define ptr @foo(ptr %ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: je .LBB0_1
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; CHECK-NEXT: # %bb.2: # %if.end
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; CHECK-NEXT: incq %rdi
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; CHECK-NEXT: jmp qux@PLT # TAILCALL
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; CHECK-NEXT: .LBB0_1: # %if.then
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset %rbx, -48
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; CHECK-NEXT: .cfi_offset %r12, -40
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; CHECK-NEXT: .cfi_offset %r13, -32
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; CHECK-NEXT: .cfi_offset %r14, -24
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; CHECK-NEXT: .cfi_offset %r15, -16
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %r14
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; CHECK-NEXT: movq %rcx, %r15
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; CHECK-NEXT: movq %r8, %r12
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; CHECK-NEXT: movq %r9, %r13
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; CHECK-NEXT: callq bar@PLT
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; CHECK-NEXT: movq %rbx, %rsi
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; CHECK-NEXT: movq %r14, %rdx
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; CHECK-NEXT: movq %r15, %rcx
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; CHECK-NEXT: movq %r12, %r8
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; CHECK-NEXT: movq %r13, %r9
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; CHECK-NEXT: movq %rax, %rdi
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: .cfi_restore %rbx
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; CHECK-NEXT: .cfi_restore %r12
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; CHECK-NEXT: .cfi_restore %r13
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; CHECK-NEXT: .cfi_restore %r14
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; CHECK-NEXT: .cfi_restore %r15
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; CHECK-NEXT: incq %rdi
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; CHECK-NEXT: jmp qux@PLT # TAILCALL
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entry:
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%tobool.not = icmp eq ptr %ptr, null
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br i1 %tobool.not, label %if.then, label %if.end, !prof !5
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if.then: ; preds = %entry
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%call = tail call ptr @bar(ptr %ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%ptr.addr.0 = phi ptr [ %call, %if.then ], [ %ptr, %entry ]
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%incdec.ptr = getelementptr inbounds i8, ptr %ptr.addr.0, i64 1
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%call2 = tail call ptr @qux(ptr %incdec.ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6)
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ret ptr %call2
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}
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!5 = !{!"branch_weights", i32 1, i32 2000}
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declare ptr @bar(ptr, i64, i64, i64, i64, i64)
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declare ptr @qux(ptr, i64, i64, i64, i64, i64)
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