a78a0f8d20
The i386 psABI specifies that `__float128` has 16 byte alignment and must be passed on the stack; however, LLVM currently stores it in a stack slot that has an offset of 4. Add a custom lowering to correct this alignment to 16-byte. i386 does not specify an `__int128`, but it seems reasonable to keep the same behavior as `__float128` so this is changed as well. There also isn't a good way to distinguish whether a set of four registers came from an integer or a float. The main test demonstrating this change is `store_perturbed` in `llvm/test/CodeGen/X86/i128-fp128-abi.ll`. Referenced ABI: https://gitlab.com/x86-psABIs/i386-ABI/-/wikis/uploads/14c05f1b1e156e0e46b61bfa7c1df1e2/intel386-psABI-2020-08-07.pdf Fixes: https://github.com/llvm/llvm-project/issues/77401
151 lines
4.1 KiB
LLVM
151 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-linux-gnu %s -o - | FileCheck %s
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define i32 @branch_eq(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: jne .LBB0_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp eq i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @branch_slt(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_slt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: jge .LBB1_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB1_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp slt i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @branch_ule(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_ule:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: jb .LBB2_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB2_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp ule i64 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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define i32 @set_gt(i64 %a, i64 %b) {
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; CHECK-LABEL: set_gt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: setl %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp sgt i64 %a, %b
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%res = select i1 %cmp, i32 1, i32 0
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ret i32 %res
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}
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define i32 @test_wide(i128 %a, i128 %b) {
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; CHECK-LABEL: test_wide:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %esi, -8
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %esi
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jge .LBB4_3
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: jmp .LBB4_2
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; CHECK-NEXT: .LBB4_3: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: .LBB4_2: # %bb1
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: .cfi_def_cfa_offset 4
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; CHECK-NEXT: retl
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entry:
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%cmp = icmp slt i128 %a, %b
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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; The comparison of the low bits will be folded to a CARRY_FALSE node. Make
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; sure the code can handle that.
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define i32 @test_carry_false(i64 %a, i64 %b) {
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; CHECK-LABEL: test_carry_false:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jge .LBB5_2
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; CHECK-NEXT: # %bb.1: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB5_2: # %bb2
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: retl
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entry:
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%x = and i64 %a, -4294967296 ;0xffffffff00000000
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%y = and i64 %b, -4294967296
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%cmp = icmp slt i64 %x, %y
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 2
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}
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