440c4b705a
Previous we used sra (X, size(X)-1); xor (add (X, Y), Y). By placing sub at the end, we allow RISCV to combine sign_extend_inreg with it to form subw. Some X86 tests for Z - abs(X) seem to have improved as well. Other targets look to be a wash. I had to modify ARM's abs matching code to match from sub instead of xor. Maybe instead ISD::ABS should be made legal. I'll try that in parallel to this patch. This is an alternative to D119099 which was focused on RISCV only. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D119171
27 lines
782 B
LLVM
27 lines
782 B
LLVM
; RUN: llc < %s -mtriple=wasm32-unknown-unknown | FileCheck %s
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; Regression test for PR41149.
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define void @mod() {
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; CHECK-LABEL: mod:
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; CHECK-NEXT: .functype mod () -> ()
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; CHECK: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.load8_s 0
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; CHECK-NEXT: local.tee 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.const 31
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; CHECK-NEXT: i32.shr_s
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; CHECK-NEXT: local.tee 0
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; CHECK-NEXT: i32.xor
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.sub
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; CHECK-NEXT: i32.store8 0
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%tmp = load <4 x i8>, <4 x i8>* undef
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%tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
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%tmp3 = sub <4 x i8> zeroinitializer, %tmp
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%tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
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store <4 x i8> %tmp4, <4 x i8>* undef
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ret void
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}
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