Brox Chen dfdfc4e490

[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861) ...

Remove another build_vector pattern which takes a i16 but placed in a
VGPR_32 from true16 mode. This stop isel from generating illegal
"vgpr_32 = COPY vgpr_16".

ISel will use vgpr16 build vector pattern in true16 mode instead

2025-09-04 18:08:18 -04:00

..

AArch64

[AArch64] Add freeze(avg(x,y)) test coverage for #147696 (#156918)

2025-09-04 16:38:41 +00:00

AMDGPU

[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)

2025-09-04 18:08:18 -04:00

ARC

…

ARM

[CodeGen] Remove ExpandInlineAsm hook (#156617)

2025-09-04 09:28:11 +02:00

AVR

[Test] Add and update tests for lrint/llrint (NFC) (#152662)

2025-08-12 09:56:51 +09:00

BPF

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

CSKY

…

DirectX

[HLSL][NFC] Change line endings to LF (#156930)

2025-09-04 14:19:23 -07:00

Generic

[NVPTX] Allow more argument integer types, such as i256 and i96 (#154824)

2025-08-21 13:54:38 -07:00

Hexagon

support branch hint for AtomicExpandImpl::expandAtomicCmpXchg (#152366)

2025-09-02 09:33:28 -04:00

Inputs

…

Lanai

…

LoongArch

[LoongArch] Use xvperm.w for cross-lane access within a single vector (#151634)

2025-09-04 10:32:52 +08:00

M68k

[M68k] Fix reverse BTST condition causing opposite failure/success logic (#153086)

2025-08-20 13:45:01 -07:00

Mips

Reland "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines" (#155063)

2025-08-25 09:15:44 -07:00

MIR

[AMDGPU] Remove most uses of /dev/null in tests (#156630)

2025-09-03 16:39:29 +01:00

MLRegAlloc

…

MSP430

MSP430: Add test for llvm.sincos intrinsic (#148602)

2025-08-28 07:39:55 +09:00

NVPTX

[NVPTX] Add support for tcgen05 instructions for sm103 target (#156613)

2025-09-04 10:43:29 +05:30

PowerPC

support branch hint for AtomicExpandImpl::expandAtomicCmpXchg (#152366)

2025-09-02 09:33:28 -04:00

RISCV

[RISCV] Use arithmetic for select c, 0, simm12 even with zicond (#156957)

2025-09-04 14:51:14 -07:00

SPARC

[SPARC] Change half to use soft promotion rather than PromoteFloat (#152727)

2025-08-18 20:56:24 +02:00

SPIRV

[HLSL][NFC] Change line endings to LF (#156930)

2025-09-04 14:19:23 -07:00

SystemZ

s390x: optimize 128-bit fshl and fshr by high values (#154919)

2025-08-27 09:31:49 +02:00

Thumb

[ARM] Have custom lowering for ucmp and scmp (#149315)

2025-08-08 06:51:18 +01:00

Thumb2

[TargetLowering] Only freeze LHS and RHS if they are used multiple times in expandABD (#156193)

2025-08-31 10:30:29 +00:00

VE

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

WebAssembly

[WebAssembly] Guard use of getSymbolName with isSymbol (#156105)

2025-09-02 16:21:35 -07:00

WinCFGuard

…

WinEH

…

X86

[X86] Compute the known bits for VPMADD52L/VPMADD52H in SimplifyDemandedBitsForTargetNode (#156847)

2025-09-04 20:21:50 +08:00

XCore

…

Xtensa

[Xtensa] Add esp32/esp8266 cpus implementation. (#152409)

2025-08-12 15:17:36 +03:00