e02d081f2b
Support -march=sapphirerapids for x86. Compare with Icelake Server, it includes 14 more new features. They are amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote, enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D86503
618 lines
28 KiB
C++
618 lines
28 KiB
C++
//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise X86 hardware features.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/X86TargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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using namespace llvm;
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using namespace llvm::X86;
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namespace {
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/// Container class for CPU features.
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/// This is a constexpr reimplementation of a subset of std::bitset. It would be
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/// nice to use std::bitset directly, but it doesn't support constant
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/// initialization.
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class FeatureBitset {
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static constexpr unsigned NUM_FEATURE_WORDS =
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(X86::CPU_FEATURE_MAX + 31) / 32;
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// This cannot be a std::array, operator[] is not constexpr until C++17.
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uint32_t Bits[NUM_FEATURE_WORDS] = {};
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public:
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constexpr FeatureBitset() = default;
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constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
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for (auto I : Init)
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set(I);
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}
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bool any() const {
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return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
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}
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constexpr FeatureBitset &set(unsigned I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
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Bits[I / 32] = NewBits;
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return *this;
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}
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constexpr bool operator[](unsigned I) const {
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uint32_t Mask = uint32_t(1) << (I % 32);
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return (Bits[I / 32] & Mask) != 0;
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}
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constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I] & RHS.Bits[I];
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Bits[I] = NewBits;
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}
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return *this;
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}
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constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
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// GCC <6.2 crashes if this is written in a single statement.
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uint32_t NewBits = Bits[I] | RHS.Bits[I];
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Bits[I] = NewBits;
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}
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return *this;
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}
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// gcc 5.3 miscompiles this if we try to write this using operator&=.
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constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] & RHS.Bits[I];
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return Result;
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}
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// gcc 5.3 miscompiles this if we try to write this using operator&=.
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constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = Bits[I] | RHS.Bits[I];
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return Result;
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}
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constexpr FeatureBitset operator~() const {
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FeatureBitset Result;
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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Result.Bits[I] = ~Bits[I];
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return Result;
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}
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constexpr bool operator!=(const FeatureBitset &RHS) const {
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for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
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if (Bits[I] != RHS.Bits[I])
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return true;
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return false;
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}
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};
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struct ProcInfo {
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StringLiteral Name;
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X86::CPUKind Kind;
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unsigned KeyFeature;
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FeatureBitset Features;
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};
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struct FeatureInfo {
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StringLiteral Name;
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FeatureBitset ImpliedFeatures;
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};
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} // end anonymous namespace
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#define X86_FEATURE(ENUM, STRING) \
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static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
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#include "llvm/Support/X86TargetParser.def"
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// Pentium with MMX.
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static constexpr FeatureBitset FeaturesPentiumMMX =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// Pentium 2 and 3.
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static constexpr FeatureBitset FeaturesPentium2 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
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static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
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// Pentium 4 CPUs
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static constexpr FeatureBitset FeaturesPentium4 =
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FeaturesPentium3 | FeatureSSE2;
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static constexpr FeatureBitset FeaturesPrescott =
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FeaturesPentium4 | FeatureSSE3;
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static constexpr FeatureBitset FeaturesNocona =
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FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
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// Basic 64-bit capable CPU.
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static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
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// Intel Core CPUs
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static constexpr FeatureBitset FeaturesCore2 =
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FeaturesNocona | FeatureSAHF | FeatureSSSE3;
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static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
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static constexpr FeatureBitset FeaturesNehalem =
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FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
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static constexpr FeatureBitset FeaturesWestmere =
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FeaturesNehalem | FeaturePCLMUL;
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static constexpr FeatureBitset FeaturesSandyBridge =
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FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
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static constexpr FeatureBitset FeaturesIvyBridge =
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FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
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static constexpr FeatureBitset FeaturesHaswell =
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FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
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FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
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static constexpr FeatureBitset FeaturesBroadwell =
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FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
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// Intel Knights Landing and Knights Mill
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// Knights Landing has feature parity with Broadwell.
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static constexpr FeatureBitset FeaturesKNL =
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FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
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static constexpr FeatureBitset FeaturesKNM =
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FeaturesKNL | FeatureAVX512VPOPCNTDQ;
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// Intel Skylake processors.
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static constexpr FeatureBitset FeaturesSkylakeClient =
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FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
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FeatureXSAVES | FeatureSGX;
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// SkylakeServer inherits all SkylakeClient features except SGX.
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// FIXME: That doesn't match gcc.
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static constexpr FeatureBitset FeaturesSkylakeServer =
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(FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
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FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
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FeaturePKU;
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static constexpr FeatureBitset FeaturesCascadeLake =
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FeaturesSkylakeServer | FeatureAVX512VNNI;
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static constexpr FeatureBitset FeaturesCooperLake =
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FeaturesCascadeLake | FeatureAVX512BF16;
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// Intel 10nm processors.
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static constexpr FeatureBitset FeaturesCannonlake =
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FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
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FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
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FeaturePKU | FeatureSHA;
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static constexpr FeatureBitset FeaturesICLClient =
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FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
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FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
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FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
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static constexpr FeatureBitset FeaturesICLServer =
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FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
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static constexpr FeatureBitset FeaturesTigerlake =
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FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
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FeatureMOVDIRI | FeatureSHSTK;
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static constexpr FeatureBitset FeaturesSapphireRapids =
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FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
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FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | FeatureENQCMD |
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FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE |
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FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
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// Intel Atom processors.
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// Bonnell has feature parity with Core2 and adds MOVBE.
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static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
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// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
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static constexpr FeatureBitset FeaturesSilvermont =
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FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
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static constexpr FeatureBitset FeaturesGoldmont =
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FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
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FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
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FeatureXSAVEOPT | FeatureXSAVES;
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static constexpr FeatureBitset FeaturesGoldmontPlus =
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FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
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static constexpr FeatureBitset FeaturesTremont =
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FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
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// Geode Processor.
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static constexpr FeatureBitset FeaturesGeode =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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// K6 processor.
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static constexpr FeatureBitset FeaturesK6 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
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// K7 and K8 architecture processors.
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static constexpr FeatureBitset FeaturesAthlon =
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FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
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static constexpr FeatureBitset FeaturesAthlonXP =
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FeaturesAthlon | FeatureFXSR | FeatureSSE;
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static constexpr FeatureBitset FeaturesK8 =
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FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
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static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
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static constexpr FeatureBitset FeaturesAMDFAM10 =
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FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
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FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
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// Bobcat architecture processors.
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static constexpr FeatureBitset FeaturesBTVER1 =
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FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
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FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
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FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
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FeatureSAHF;
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static constexpr FeatureBitset FeaturesBTVER2 =
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FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
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FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
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// AMD Bulldozer architecture processors.
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static constexpr FeatureBitset FeaturesBDVER1 =
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FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
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FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
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FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
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FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
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FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
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static constexpr FeatureBitset FeaturesBDVER2 =
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FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
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static constexpr FeatureBitset FeaturesBDVER3 =
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FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
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static constexpr FeatureBitset FeaturesBDVER4 =
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FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX |
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FeatureRDRND;
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// AMD Zen architecture processors.
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static constexpr FeatureBitset FeaturesZNVER1 =
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FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
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FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
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FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
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FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
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FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
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FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
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FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
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FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
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FeatureXSAVEOPT | FeatureXSAVES;
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static constexpr FeatureBitset FeaturesZNVER2 =
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FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
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static constexpr ProcInfo Processors[] = {
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// Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
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{ {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
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// i386-generation processors.
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{ {"i386"}, CK_i386, ~0U, FeatureX87 },
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// i486-generation processors.
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{ {"i486"}, CK_i486, ~0U, FeatureX87 },
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{ {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
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{ {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
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{ {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
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// i586-generation processors, P5 microarchitecture based.
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{ {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
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{ {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
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{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
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// i686-generation processors, P6 / Pentium M microarchitecture based.
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{ {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
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{ {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
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{ {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
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{ {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
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{ {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
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{ {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
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{ {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
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{ {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
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// Netburst microarchitecture based processors.
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{ {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
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{ {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
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{ {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
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{ {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
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// Core microarchitecture based processors.
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{ {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
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{ {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
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// Atom processors
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{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
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{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
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{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
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{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
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{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
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{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
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{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
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// Nehalem microarchitecture based processors.
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{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
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{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
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// Westmere microarchitecture based processors.
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{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
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// Sandy Bridge microarchitecture based processors.
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{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
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{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
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// Ivy Bridge microarchitecture based processors.
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{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
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{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
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// Haswell microarchitecture based processors.
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{ {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
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{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
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// Broadwell microarchitecture based processors.
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{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
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// Skylake client microarchitecture based processors.
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{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
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// Skylake server microarchitecture based processors.
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{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
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{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
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// Cascadelake Server microarchitecture based processors.
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{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
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// Cooperlake Server microarchitecture based processors.
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{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
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// Cannonlake client microarchitecture based processors.
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{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
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// Icelake client microarchitecture based processors.
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{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
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// Icelake server microarchitecture based processors.
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{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
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// Tigerlake microarchitecture based processors.
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{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
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// Sapphire Rapids microarchitecture based processors.
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{ {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
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// Knights Landing processor.
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{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
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// Knights Mill processor.
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{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
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// Lakemont microarchitecture based processors.
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{ {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
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// K6 architecture processors.
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{ {"k6"}, CK_K6, ~0U, FeaturesK6 },
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{ {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
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{ {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
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// K7 architecture processors.
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{ {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
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{ {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
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{ {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
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{ {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
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{ {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
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// K8 architecture processors.
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{ {"k8"}, CK_K8, ~0U, FeaturesK8 },
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{ {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
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{ {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
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{ {"opteron"}, CK_K8, ~0U, FeaturesK8 },
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{ {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
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{ {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
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{ {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
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{ {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
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{ {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
|
|
// Bobcat architecture processors.
|
|
{ {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
|
|
{ {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
|
|
// Bulldozer architecture processors.
|
|
{ {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
|
|
{ {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
|
|
{ {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
|
|
{ {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
|
|
// Zen architecture processors.
|
|
{ {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
|
|
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
|
|
// Generic 64-bit processor.
|
|
{ {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
|
|
// Geode processors.
|
|
{ {"geode"}, CK_Geode, ~0U, FeaturesGeode },
|
|
};
|
|
|
|
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
|
|
for (const auto &P : Processors)
|
|
if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
|
|
return P.Kind;
|
|
|
|
return CK_None;
|
|
}
|
|
|
|
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
|
|
bool Only64Bit) {
|
|
for (const auto &P : Processors)
|
|
if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
|
|
Values.emplace_back(P.Name);
|
|
}
|
|
|
|
ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
|
|
// FIXME: Can we avoid a linear search here? The table might be sorted by
|
|
// CPUKind so we could binary search?
|
|
for (const auto &P : Processors) {
|
|
if (P.Kind == Kind) {
|
|
assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
|
|
return static_cast<ProcessorFeatures>(P.KeyFeature);
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Unable to find CPU kind!");
|
|
}
|
|
|
|
// Features with no dependencies.
|
|
static constexpr FeatureBitset ImpliedFeatures64BIT = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesADX = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesBMI = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCLWB = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesLWP = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPKU = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRDPID = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRDRND = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRTM = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesSAHF = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesSGX = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesTBM = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesX87 = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
|
|
|
|
// Not really CPU features, but need to be in the table because clang uses
|
|
// target features to communicate them to the backend.
|
|
static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
|
|
|
|
// XSAVE features are dependent on basic XSAVE.
|
|
static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
|
|
static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
|
|
static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
|
|
|
|
// MMX->3DNOW->3DNOWA chain.
|
|
static constexpr FeatureBitset ImpliedFeaturesMMX = {};
|
|
static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
|
|
static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
|
|
|
|
// SSE/AVX/AVX512F chain.
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
|
|
static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512F =
|
|
FeatureAVX2 | FeatureF16C | FeatureFMA;
|
|
|
|
// Vector extensions that build on SSE or AVX.
|
|
static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
|
|
static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
|
|
static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
|
|
static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
|
|
static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
|
|
static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
|
|
static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
|
|
static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ =
|
|
FeatureAVX | FeaturePCLMUL;
|
|
|
|
// AVX512 features.
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
|
|
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT =
|
|
FeatureAVX512F;
|
|
|
|
// FIXME: These two aren't really implemented and just exist in the feature
|
|
// list for __builtin_cpu_supports. So omit their dependencies.
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
|
|
|
|
// SSE4_A->FMA4->XOP chain.
|
|
static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSSE3;
|
|
static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
|
|
static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
|
|
|
|
// AMX Features
|
|
static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
|
|
static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
|
|
static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
|
|
|
|
static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
|
|
#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
|
|
#include "llvm/Support/X86TargetParser.def"
|
|
};
|
|
|
|
void llvm::X86::getFeaturesForCPU(StringRef CPU,
|
|
SmallVectorImpl<StringRef> &EnabledFeatures) {
|
|
auto I = llvm::find_if(Processors,
|
|
[&](const ProcInfo &P) { return P.Name == CPU; });
|
|
assert(I != std::end(Processors) && "Processor not found!");
|
|
|
|
FeatureBitset Bits = I->Features;
|
|
|
|
// Remove the 64-bit feature which we only use to validate if a CPU can
|
|
// be used with 64-bit mode.
|
|
Bits &= ~Feature64BIT;
|
|
|
|
// Add the string version of all set bits.
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if (Bits[i] && !FeatureInfos[i].Name.empty())
|
|
EnabledFeatures.push_back(FeatureInfos[i].Name);
|
|
}
|
|
|
|
// For each feature that is (transitively) implied by this feature, set it.
|
|
static void getImpliedEnabledFeatures(FeatureBitset &Bits,
|
|
const FeatureBitset &Implies) {
|
|
// Fast path: Implies is often empty.
|
|
if (!Implies.any())
|
|
return;
|
|
FeatureBitset Prev;
|
|
Bits |= Implies;
|
|
do {
|
|
Prev = Bits;
|
|
for (unsigned i = CPU_FEATURE_MAX; i;)
|
|
if (Bits[--i])
|
|
Bits |= FeatureInfos[i].ImpliedFeatures;
|
|
} while (Prev != Bits);
|
|
}
|
|
|
|
/// Create bit vector of features that are implied disabled if the feature
|
|
/// passed in Value is disabled.
|
|
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
|
|
// Check all features looking for any dependent on this feature. If we find
|
|
// one, mark it and recursively find any feature that depend on it.
|
|
FeatureBitset Prev;
|
|
Bits.set(Value);
|
|
do {
|
|
Prev = Bits;
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
|
|
Bits.set(i);
|
|
} while (Prev != Bits);
|
|
}
|
|
|
|
void llvm::X86::updateImpliedFeatures(
|
|
StringRef Feature, bool Enabled,
|
|
StringMap<bool> &Features) {
|
|
auto I = llvm::find_if(
|
|
FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
|
|
if (I == std::end(FeatureInfos)) {
|
|
// FIXME: This shouldn't happen, but may not have all features in the table
|
|
// yet.
|
|
return;
|
|
}
|
|
|
|
FeatureBitset ImpliedBits;
|
|
if (Enabled)
|
|
getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
|
|
else
|
|
getImpliedDisabledFeatures(ImpliedBits,
|
|
std::distance(std::begin(FeatureInfos), I));
|
|
|
|
// Update the map entry for all implied features.
|
|
for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
|
|
if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
|
|
Features[FeatureInfos[i].Name] = Enabled;
|
|
}
|