420a5de1a4
When using the `amdgcn.init.whole.wave` intrinsic, we add dummy VGPR arguments with the purpose of preserving their inactive lanes. The pattern may look something like this: ``` entry: call amdgcn.init.whole.wave branch to shader or tail shader: $vInactive = IMPLICIT_DEF ; Tells regalloc it's safe to use the active lanes actual code... tail: call amdgcn.cs.chain [...], implicit $vInactive ``` We should not report these VGPRs in the `.vgpr_count` metadata. This patch achieves that goal by ignoring meta instructions and calls. This should be safe since if those registers are actually used in any other context, they will be counted there. The same reasoning applies in the general case, so we don't explicitly check for the existence of `init.whole.wave`. This is a reworked version of #133242, which was reverted in #144039 and split into smaller bits.
47 lines
2.0 KiB
LLVM
47 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s
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; CHECK-LABEL: .shader_functions:
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; Make sure that .vgpr_count doesn't include the %inactive.vgpr registers.
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; CHECK-LABEL: leaf_shader:
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; CHECK: .vgpr_count: 0xc{{$}}
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; Function without calls.
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define amdgpu_cs_chain void @_leaf_shader(ptr %output.ptr, i32 inreg %input.value,
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i32 %active.vgpr1, i32 %active.vgpr2,
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i32 %inactive.vgpr1, i32 %inactive.vgpr2, i32 %inactive.vgpr3,
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i32 %inactive.vgpr4, i32 %inactive.vgpr5, i32 %inactive.vgpr6)
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local_unnamed_addr {
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entry:
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%dead.val = call i32 @llvm.amdgcn.dead.i32()
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%is.whole.wave = call i1 @llvm.amdgcn.init.whole.wave()
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br i1 %is.whole.wave, label %compute, label %merge
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compute:
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; Perform a more complex computation using active VGPRs
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%square = mul i32 %active.vgpr1, %active.vgpr1
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%product = mul i32 %square, %active.vgpr2
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%sum = add i32 %product, %input.value
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%result = add i32 %sum, 42
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br label %merge
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merge:
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%final.result = phi i32 [ 0, %entry ], [ %result, %compute ]
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%final.inactive1 = phi i32 [ %inactive.vgpr1, %entry ], [ %dead.val, %compute ]
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%final.inactive2 = phi i32 [ %inactive.vgpr2, %entry ], [ %dead.val, %compute ]
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%final.inactive3 = phi i32 [ %inactive.vgpr3, %entry ], [ %dead.val, %compute ]
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%final.inactive4 = phi i32 [ %inactive.vgpr4, %entry ], [ %dead.val, %compute ]
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%final.inactive5 = phi i32 [ %inactive.vgpr5, %entry ], [ %dead.val, %compute ]
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%final.inactive6 = phi i32 [ %inactive.vgpr6, %entry ], [ %dead.val, %compute ]
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store i32 %final.result, ptr %output.ptr, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.dead.i32()
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declare i1 @llvm.amdgcn.init.whole.wave()
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declare void @llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32 immarg, ...)
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declare amdgpu_cs_chain void @retry_vgpr_alloc.v4i32(<4 x i32> inreg)
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