fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
55 lines
2.6 KiB
LLVM
55 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX906
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX942
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 < %s | FileCheck %s --check-prefixes=GCN,GFX12
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declare float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 %clamp)
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; GCN-LABEL: {{^}}test_llvm_amdgcn_fdot2_clamp
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; GFX9: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX10: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX12: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_fdot2_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x half>, ptr addrspace(1) %a
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%b.val = load <2 x half>, ptr addrspace(1) %b
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%c.val = load float, ptr addrspace(1) %c
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%r.val = call float @llvm.amdgcn.fdot2(<2 x half> %a.val, <2 x half> %b.val, float %c.val, i1 1)
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store float %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_fdot2_no_clamp
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; GFX906: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX942: v_dot2c_f32_f16_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX10: {{v_dot2c_f32_f16|v_dot2acc_f32_f16}} v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX12: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_fdot2_no_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x half>, ptr addrspace(1) %a
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%b.val = load <2 x half>, ptr addrspace(1) %b
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%c.val = load float, ptr addrspace(1) %c
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%r.val = call float @llvm.amdgcn.fdot2(<2 x half> %a.val, <2 x half> %b.val, float %c.val, i1 0)
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store float %r.val, ptr addrspace(1) %r
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ret void
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}
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; GFX9-LABEL: {{^}}fdot2_inline_literal
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; GFX906: v_dot2_f32_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 1.0
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; GFX942: v_dot2c_f32_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX12: v_dot2_f32_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}
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define float @fdot2_inline_literal(<2 x half> %a, <2 x half> %b) {
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%ret = tail call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float 1.0, i1 false)
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ret float %ret
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}
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