fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
139 lines
6.4 KiB
LLVM
139 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck -check-prefixes=CHECK,SI %s
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;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck -check-prefixes=CHECK,VI %s
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define amdgpu_ps void @buffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {
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; CHECK-LABEL: buffer_store:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: v_mov_b32_e32 v12, 0
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v12, s[0:3], 0 idxen
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; CHECK-NEXT: buffer_store_format_xyzw v[4:7], v12, s[0:3], 0 idxen glc
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; CHECK-NEXT: buffer_store_format_xyzw v[8:11], v12, s[0:3], 0 idxen slc
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)
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ret void
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}
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define amdgpu_ps void @buffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {
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; CHECK-LABEL: buffer_store_immoffs:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen offset:42
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float>, i32) {
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; CHECK-LABEL: buffer_store_idx:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float>, i32) {
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; CHECK-LABEL: buffer_store_ofs:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: v_mov_b32_e32 v5, v4
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; CHECK-NEXT: v_mov_b32_e32 v4, s4
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 0, i32 %2, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
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; CHECK-LABEL: buffer_store_both:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 %3, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_both_reversed(ptr addrspace(8) inreg, <4 x float>, i32, i32) {
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; CHECK-LABEL: buffer_store_both_reversed:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: v_mov_b32_e32 v6, v4
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; CHECK-NEXT: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %3, i32 %2, i32 0, i32 0)
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ret void
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}
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; Ideally, the register allocator would avoid the wait here
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;
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define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float>, i32, i32, i32) {
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; SI-LABEL: buffer_store_wait:
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; SI: ; %bb.0: ; %main_body
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; SI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: buffer_store_wait:
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; VI: ; %bb.0: ; %main_body
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; VI-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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; VI-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
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; VI-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %1, ptr addrspace(8) %0, i32 %2, i32 0, i32 0, i32 0)
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%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 %3, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> %data, ptr addrspace(8) %0, i32 %4, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %index) {
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; CHECK-LABEL: buffer_store_x1:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.f32(float %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_x1_i32(ptr addrspace(8) inreg %rsrc, i32 %data, i32 %index) {
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; CHECK-LABEL: buffer_store_x1_i32:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: buffer_store_format_x v0, v1, s[0:3], 0 idxen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.i32(i32 %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %index) {
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; CHECK-LABEL: buffer_store_x2:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
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; CHECK-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f32(<2 x float> %data, ptr addrspace(8) %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.struct.ptr.buffer.store.format.f32(float, ptr addrspace(8), i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.ptr.buffer.store.format.i32(i32, ptr addrspace(8), i32, i32, i32, i32) #0
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declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8), i32, i32, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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