9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
20 lines
749 B
LLVM
20 lines
749 B
LLVM
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx908 | FileCheck %s --check-prefixes=GCN,GFX908
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s --check-prefixes=GCN,GFX90A
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; GCN-LABEL: {{^}}mul_legacy
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; GFX908: v_mul_legacy_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX90A: v_mul_legacy_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @mul_legacy(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b) {
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entry:
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%a.val = load volatile float, ptr addrspace(1) %a
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%b.val = load volatile float, ptr addrspace(1) %b
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%r.val = call float @llvm.pow.f32(float %a.val, float %b.val)
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store float %r.val, ptr addrspace(1) %r
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ret void
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}
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declare float @llvm.pow.f32(float ,float ) readonly
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