421 lines
14 KiB
LLVM
421 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefixes=GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX1250 %s
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define amdgpu_ps float @mad_i32_vvv(i32 %a, i32 %b, i32 %c) {
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; GFX9-LABEL: mad_i32_vvv:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vvv:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vvv:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v3, v1
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; GFX11-NEXT: v_mov_b32_e32 v4, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v3, v[2:3]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vvv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v2
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
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; GFX9-LABEL: mad_i32_sss:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_mul_i32 s0, s0, s1
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; GFX9-NEXT: s_add_i32 s0, s0, s2
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_sss:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mul_i32 s0, s0, s1
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; GFX10-NEXT: s_add_i32 s0, s0, s2
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_sss:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mul_i32 s0, s0, s1
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; GFX11-NEXT: s_add_i32 s0, s0, s2
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_sss:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_mul_i32 s0, s0, s1
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; GFX1250-NEXT: s_add_co_i32 s0, s0, s2
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; GFX1250-NEXT: v_mov_b32_e32 v0, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vvc(i32 %a, i32 %b) {
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; GFX9-LABEL: mad_i32_vvc:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, 42
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vvc:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 42
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vvc:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v1
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; GFX11-NEXT: v_mov_b32_e32 v3, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 42
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vvc:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 42
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, 42
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vvi(i32 %a, i32 %b) {
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; GFX9-LABEL: mad_i32_vvi:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v2, 0x12d687
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; GFX9-NEXT: v_mov_b32_e32 v3, 0
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vvi:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 0x12d687
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vvi:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v1
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; GFX11-NEXT: v_mov_b32_e32 v3, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 0x12d687
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vvi:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0x12d687
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, 1234567
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vvi_neg(i32 %a, i32 %b) {
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; GFX9-LABEL: mad_i32_vvi_neg:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v2, 0xffed2979
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; GFX9-NEXT: v_mov_b32_e32 v3, -1
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vvi_neg:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 0xffffffffffed2979
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vvi_neg:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v1
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; GFX11-NEXT: v_mov_b32_e32 v3, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 0xffffffffffed2979
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vvi_neg:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0xffed2979
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, -1234567
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {
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; GFX9-LABEL: mad_i32_vcv:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 42, v[1:2]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vcv:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 42, v[1:2]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vcv:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, 42, v[1:2]
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; GFX11-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vcv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, 42, v1
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, 42
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vcc(i32 %a) {
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; GFX9-LABEL: mad_i32_vcc:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 42, 43
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vcc:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 42, 43
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vcc:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, 42, 43
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vcc:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, 42, 43
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, 42
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%add = add i32 %mul, 43
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
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; GFX9-LABEL: mad_i32_vvs:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, s[0:1]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vvs:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, s[0:1]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vvs:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v1
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; GFX11-NEXT: v_mov_b32_e32 v3, v0
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, s[0:1]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vvs:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, v1, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {
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; GFX9-LABEL: mad_i32_vsv:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, s0, v[1:2]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vsv:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, v[1:2]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vsv:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
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; GFX11-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vsv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, s0, v1
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_svv(i32 inreg %a, i32 %b, i32 %c) {
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; GFX9-LABEL: mad_i32_svv:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s0, v0, v[1:2]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_svv:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, v[1:2]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_svv:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, s0, v0, v[1:2]
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; GFX11-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_svv:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, s0, v0, v1
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {
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; GFX9-LABEL: mad_i32_vss:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, s0
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; GFX9-NEXT: v_add_u32_e32 v0, s1, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_vss:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mov_b32 s2, s1
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, s[2:3]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_vss:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v0
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; GFX11-NEXT: s_mov_b32 s2, s1
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, s0, s[2:3]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_vss:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, v0, s0, s1
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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%cast = bitcast i32 %add to float
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ret float %cast
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}
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define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {
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; GFX9-LABEL: mad_i32_svs:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mul_lo_u32 v0, s0, v0
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; GFX9-NEXT: v_add_u32_e32 v0, s1, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_i32_svs:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mov_b32 s2, s1
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; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, s[2:3]
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; GFX10-NEXT: ; return to shader part epilog
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;
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; GFX11-LABEL: mad_i32_svs:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v2, v0
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; GFX11-NEXT: s_mov_b32 s2, s1
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; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, s0, v2, s[2:3]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: mad_i32_svs:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: v_mad_u32 v0, s0, v0, s1
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%mul = mul i32 %a, %b
|
|
%add = add i32 %mul, %c
|
|
%cast = bitcast i32 %add to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mad_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
|
|
; GFX9-LABEL: mad_i32_ssv:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_mul_i32 s0, s0, s1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
|
|
; GFX9-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: mad_i32_ssv:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, s1, v[0:1]
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: mad_i32_ssv:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, s0, s1, v[0:1]
|
|
; GFX11-NEXT: v_mov_b32_e32 v0, v1
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-LABEL: mad_i32_ssv:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: v_mad_u32 v0, s0, s1, v0
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%mul = mul i32 %a, %b
|
|
%add = add i32 %mul, %c
|
|
%cast = bitcast i32 %add to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {
|
|
; GFX9-LABEL: mad_i32_vvv_multiuse:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, v1, v2
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10-LABEL: mad_i32_vvv_multiuse:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: v_mul_lo_u32 v1, v0, v1
|
|
; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v2
|
|
; GFX10-NEXT: flat_store_dword v[0:1], v1
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-LABEL: mad_i32_vvv_multiuse:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_mul_lo_u32 v1, v0, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, v1, v2
|
|
; GFX11-NEXT: flat_store_b32 v[0:1], v1
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-LABEL: mad_i32_vvv_multiuse:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: v_mul_lo_u32 v1, v0, v1
|
|
; GFX1250-NEXT: v_add_nc_u32_e32 v0, v1, v2
|
|
; GFX1250-NEXT: flat_store_b32 v[0:1], v1 scope:SCOPE_SE
|
|
; GFX1250-NEXT: s_wait_dscnt 0x0
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%mul = mul i32 %a, %b
|
|
%add = add i32 %mul, %c
|
|
store i32 %mul, ptr poison
|
|
%cast = bitcast i32 %add to float
|
|
ret float %cast
|
|
}
|