c4b1557097
Fold sequences where we extract a bunch of contiguous bits from a value, merge them into the low bit and then check if the low bits are zero or not. Usually the and would be on the outside (the leaves) of the expression, but the DAG canonicalizes it to a single `and` at the root of the expression. The reason I put this in DAGCombiner instead of the target combiner is because this is a generic, valid transform that's also fairly niche, so there isn't much risk of a combine loop I think. See #136727
124 lines
3.5 KiB
LLVM
124 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -O3 -mtriple=amdgcn -mcpu=fiji %s -o - | FileCheck %s
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define i1 @basic_eq_i16_3x5(i16 %arg) {
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; CHECK-LABEL: basic_eq_i16_3x5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; CHECK-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%a = and i16 %arg, 31
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%sh5 = lshr i16 %arg, 5
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%b = and i16 %sh5, 31
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%or = or i16 %a, %b
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%sh10 = lshr i16 %arg, 10
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%c = and i16 %sh10, 31
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%or1 = or i16 %or, %c
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%cmp = icmp eq i16 %or1, 0
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ret i1 %cmp
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}
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define i1 @basic_eq_i32_3x5(i32 %arg) {
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; CHECK-LABEL: basic_eq_i32_3x5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%a = and i32 %arg, 31
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%sh5 = lshr i32 %arg, 5
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%b = and i32 %sh5, 31
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%or = or i32 %a, %b
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%sh10 = lshr i32 %arg, 10
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%c = and i32 %sh10, 31
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%or1 = or i32 %or, %c
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%cmp = icmp eq i32 %or1, 0
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ret i1 %cmp
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}
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define i1 @basic_eq_i64_3x5(i64 %arg) {
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; CHECK-LABEL: basic_eq_i64_3x5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%a = and i64 %arg, 31
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%sh5 = lshr i64 %arg, 5
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%b = and i64 %sh5, 31
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%or = or i64 %a, %b
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%sh10 = lshr i64 %arg, 10
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%c = and i64 %sh10, 31
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%or1 = or i64 %or, %c
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%cmp = icmp eq i64 %or1, 0
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ret i1 %cmp
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}
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define i1 @basic_ne_i32_3x5(i32 %arg) {
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; CHECK-LABEL: basic_ne_i32_3x5:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%a = and i32 %arg, 31
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%sh5 = lshr i32 %arg, 5
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%b = and i32 %sh5, 31
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%or = or i32 %a, %b
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%sh10 = lshr i32 %arg, 10
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%c = and i32 %sh10, 31
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%or1 = or i32 %or, %c
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%cmp = icmp ne i32 %or1, 0
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ret i1 %cmp
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}
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define i1 @eq_i32_3x5_holes_in_mask(i32 %arg) {
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; CHECK-LABEL: eq_i32_3x5_holes_in_mask:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7f9f, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%a = and i32 %arg, 31
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%sh5 = lshr i32 %arg, 7
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%b = and i32 %sh5, 31
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%or = or i32 %a, %b
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%sh10 = lshr i32 %arg, 10
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%c = and i32 %sh10, 31
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%or1 = or i32 %or, %c
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%cmp = icmp ne i32 %or1, 0
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ret i1 %cmp
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}
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define i1 @eq_i32_3x5_all_shifted(i32 %arg) {
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; CHECK-LABEL: eq_i32_3x5_all_shifted:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0x7ffc, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%sh2 = lshr i32 %arg, 2
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%a = and i32 %sh2, 31
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%sh5 = lshr i32 %arg, 7
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%b = and i32 %sh5, 31
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%or = or i32 %a, %b
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%sh10 = lshr i32 %arg, 10
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%c = and i32 %sh10, 31
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%or1 = or i32 %or, %c
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%cmp = icmp ne i32 %or1, 0
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ret i1 %cmp
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}
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