9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
112 lines
2.8 KiB
LLVM
112 lines
2.8 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc -mtriple=amdgcn < %s -debug-only=igrouplp 2>&1 | FileCheck --check-prefixes=GCN %s
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; Inverted 1008: 01111110000
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; GCN: After Inverting, SchedGroup Mask: 1008
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define amdgpu_kernel void @invert1() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 1) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 2044: 11111111100
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; GCN: After Inverting, SchedGroup Mask: 2044
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define amdgpu_kernel void @invert2() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 2) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 2042: 11111111010
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; GCN: After Inverting, SchedGroup Mask: 2042
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define amdgpu_kernel void @invert4() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 4) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 2038: 11111110110
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; GCN: After Inverting, SchedGroup Mask: 2038
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define amdgpu_kernel void @invert8() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 8) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1935: 11110001111
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; GCN: After Inverting, SchedGroup Mask: 1935
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define amdgpu_kernel void @invert16() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 16) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1999: 11111001111
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; GCN: After Inverting, SchedGroup Mask: 1999
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define amdgpu_kernel void @invert32() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 32) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1967: 11110101111
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; GCN: After Inverting, SchedGroup Mask: 1967
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define amdgpu_kernel void @invert64() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 64) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1151: 10001111111
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; GCN: After Inverting, SchedGroup Mask: 1151
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define amdgpu_kernel void @invert128() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 128) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1663: 11001111111
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; GCN: After Inverting, SchedGroup Mask: 1663
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define amdgpu_kernel void @invert256() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 256) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1407: 10101111111
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; GCN: After Inverting, SchedGroup Mask: 1407
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define amdgpu_kernel void @invert512() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 512) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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; Inverted 1022: 01111111110
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; GCN: After Inverting, SchedGroup Mask: 1022
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define amdgpu_kernel void @invert1024() #0 {
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entry:
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call void @llvm.amdgcn.sched.barrier(i32 1024) #1
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call void @llvm.amdcn.s.nop(i16 0) #1
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ret void
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}
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declare void @llvm.amdgcn.sched.barrier(i32) #1
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declare void @llvm.amdcn.s.nop(i16) #1
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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