llvm-project/llvm/test/CodeGen/AMDGPU/vectorize-buffer-fat-pointer.ll
Piotr Sobczak 170c0dac44
[AMDGPU] Fix edge case of buffer OOB handling (#115479)
Strengthen out-of-bounds guarantees for buffer accesses by disallowing
buffer accesses with alignment lower than natural alignment.

This is needed to specifically address the edge case where an access
starts out-of-bounds and then enters in-bounds, as the hardware would
treat the entire access as being out-of-bounds. This is normally not
needed for most users, but at least one graphics device extension
(VK_EXT_robustness2) has very strict requirements - in-bounds accesses
must return correct value, and out-of-bounds accesses must return zero.

The direct consequence of the patch is that a buffer access at negative
address is not merged by load-store-vectorizer with one at a positive
address, which fixes a CTS test.

Targets that do not care about the new behavior are advised to use the
new target feature relaxed-buffer-oob-mode that maintains the state from
before the patch.
2025-03-07 08:56:44 +01:00

32 lines
1.2 KiB
LLVM

; RUN: opt -S -mtriple=amdgcn-- -passes=load-store-vectorizer < %s | FileCheck -check-prefix=OPT %s
; OPT-LABEL: @buffer_fat_ptrs(
define void @buffer_fat_ptrs(ptr addrspace(7) %out) {
entry:
%a1 = getelementptr i32, ptr addrspace(7) %out, i32 1
%a2 = getelementptr i32, ptr addrspace(7) %out, i32 2
%a3 = getelementptr i32, ptr addrspace(7) %out, i32 3
; OPT: store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr addrspace(7) %out, align 16
store i32 0, ptr addrspace(7) %out, align 16
store i32 1, ptr addrspace(7) %a1, align 4
store i32 2, ptr addrspace(7) %a2, align 8
store i32 3, ptr addrspace(7) %a3, align 4
ret void
}
; OPT-LABEL: @buffer_strided_ptrs(
define void @buffer_strided_ptrs(ptr addrspace(9) %out) {
entry:
%a1 = getelementptr i32, ptr addrspace(9) %out, i32 1
%a2 = getelementptr i32, ptr addrspace(9) %out, i32 2
%a3 = getelementptr i32, ptr addrspace(9) %out, i32 3
; OPT: store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, ptr addrspace(9) %out, align 16
store i32 0, ptr addrspace(9) %out, align 16
store i32 1, ptr addrspace(9) %a1, align 4
store i32 2, ptr addrspace(9) %a2, align 8
store i32 3, ptr addrspace(9) %a3, align 4
ret void
}