b922a36211
PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to provide scheduling information. This patch re-writes the tablegen file to define the scheduling information in the new SchedModel way, which can bring improvements to some benchmarks. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D154488
32 lines
932 B
LLVM
32 lines
932 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-unknown \
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; RUN: < %s 2>&1 | FileCheck --check-prefix=CHECK-LE %s
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; RUN: llc -mtriple=powerpc64-unknown-unknown \
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; RUN: < %s 2>&1 | FileCheck %s
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define float @bar(ptr %fp) {
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; CHECK-LE-LABEL: bar:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: lwz 3, 0(3)
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; CHECK-LE-NEXT: mtfprd 0, 3
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; CHECK-LE-NEXT: cmpd 7, 3, 3
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; CHECK-LE-NEXT: bne- 7, .+4
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; CHECK-LE-NEXT: isync
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; CHECK-LE-NEXT: xxsldwi 0, 0, 0, 1
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; CHECK-LE-NEXT: xscvspdpn 1, 0
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; CHECK-LE-NEXT: blr
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;
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: cmpd 7, 3, 3
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; CHECK-NEXT: bne- 7, .+4
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; CHECK-NEXT: isync
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; CHECK-NEXT: stw 3, -4(1)
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; CHECK-NEXT: lfs 1, -4(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load atomic float, ptr %fp acquire, align 4
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ret float %0
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}
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