5ecd363295
This reverts commit 122efef8ee9be57055d204d52c38700fe933c033. - Patch fixed to not reuse definitions from predecessors in EH landing pads. - Late review suggestions (by MaskRay) have been addressed. - M68k/pipeline.ll test updated. - Init captures added in processBlock() to avoid capturing structured bindings. - RISCV has this disabled for now. Original commit message: A new pass MachineLateInstrsCleanup is added to be run after PEI. This is a simple pass that removes redundant and identical instructions whenever found by scanning the MF once while keeping track of register definitions in a map. These instructions are typically immediate loads resulting from rematerialization, and address loads emitted by target in eliminateFrameInde(). This is enabled by default, but a target could easily disable it by means of 'disablePass(&MachineLateInstrsCleanupID);'. This late cleanup is naturally not "optimal" in removing instructions as it is done by looking at phys-regs, but still quite effective. It would be desirable to improve other parts of CodeGen and avoid these redundant instructions in the first place, but there are no ideas for this yet. Differential Revision: https://reviews.llvm.org/D123394 Reviewed By: RKSimon, foad, craig.topper, arsenm, asb
69 lines
2.4 KiB
LLVM
69 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mcpu=pwr9 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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define dso_local void @wibble(ptr nocapture readonly %arg, i32 signext %arg1, ptr nocapture %arg2, ptr nocapture %arg3) {
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; CHECK-LABEL: wibble:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: lfs 0, 0(3)
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; CHECK-NEXT: li 7, 7
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; CHECK-NEXT: cmpwi 4, 2
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; CHECK-NEXT: xsaddsp 0, 0, 0
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; CHECK-NEXT: blt 0, .LBB0_5
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; CHECK-NEXT: # %bb.1: # %bb6
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; CHECK-NEXT: clrldi 4, 4, 32
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; CHECK-NEXT: addi 4, 4, -1
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; CHECK-NEXT: mtctr 4
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; CHECK-NEXT: li 4, 8
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_2: # %bb11
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; CHECK-NEXT: #
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; CHECK-NEXT: iselgt 7, 4, 7
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; CHECK-NEXT: addi 4, 4, 1
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; CHECK-NEXT: bdz .LBB0_5
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; CHECK-NEXT: .LBB0_3: # %bb11
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; CHECK-NEXT: #
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; CHECK-NEXT: lfsu 1, 4(3)
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; CHECK-NEXT: fcmpu 0, 1, 0
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; CHECK-NEXT: ble 0, .LBB0_2
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; CHECK-NEXT: # %bb.4:
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; CHECK-NEXT: xsaddsp 0, 1, 1
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_5: # %bb8
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; CHECK-NEXT: stw 7, 0(5)
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; CHECK-NEXT: stfs 0, 0(6)
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; CHECK-NEXT: blr
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bb:
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%tmp = load float, ptr %arg, align 4
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%tmp4 = fmul float %tmp, 2.000000e+00
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%tmp5 = icmp sgt i32 %arg1, 1
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br i1 %tmp5, label %bb6, label %bb8
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bb6: ; preds = %bb
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%tmp7 = zext i32 %arg1 to i64
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br label %bb11
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bb8: ; preds = %bb11, %bb
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%tmp9 = phi float [ %tmp4, %bb ], [ %tmp19, %bb11 ]
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%tmp10 = phi i32 [ 7, %bb ], [ %tmp22, %bb11 ]
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store i32 %tmp10, ptr %arg2, align 4
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store float %tmp9, ptr %arg3, align 4
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ret void
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bb11: ; preds = %bb11, %bb6
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%tmp12 = phi i64 [ 1, %bb6 ], [ %tmp23, %bb11 ]
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%tmp13 = phi i32 [ 7, %bb6 ], [ %tmp22, %bb11 ]
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%tmp14 = phi float [ %tmp4, %bb6 ], [ %tmp19, %bb11 ]
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%tmp15 = getelementptr inbounds float, ptr %arg, i64 %tmp12
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%tmp16 = load float, ptr %tmp15, align 4
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%tmp17 = fcmp ogt float %tmp16, %tmp14
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%tmp18 = fmul float %tmp16, 2.000000e+00
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%tmp19 = select i1 %tmp17, float %tmp18, float %tmp14
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%tmp20 = trunc i64 %tmp12 to i32
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%tmp21 = add i32 %tmp20, 7
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%tmp22 = select i1 %tmp17, i32 %tmp21, i32 %tmp13
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%tmp23 = add nuw nsw i64 %tmp12, 1
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%tmp24 = icmp eq i64 %tmp23, %tmp7
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br i1 %tmp24, label %bb8, label %bb11
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}
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