335e8bf100
This patch changes the PowerPC backend to generate VSX load/store instructions for all vector loads/stores on Power8 and earlier (LE) instead of VMX load/store instructions. The reason for this change is because VMX instructions require the vector to be 16-byte aligned. So, a vector load/store will fail with VMX instructions if the vector is misaligned. Also, `gcc` generates VSX instructions in this situation which allow for unaligned access but require a swap instruction after loading/before storing. This is not an issue for BE because we already emit VSX instructions since no swap is required. And this is not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which allow for unaligned access and do not require swaps. This patch also delays the VSX load/store for LE combines until after LegalizeOps to prioritize other load/store combines. Reviewed By: #powerpc, stefanp Differential Revision: https://reviews.llvm.org/D127309
176 lines
5.1 KiB
LLVM
176 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s
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define float @absf(float %a) {
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; CHECK-LABEL: absf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsabsdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast float %a to i32
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%and = and i32 %conv, 2147483647
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @absd(double %a) {
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; CHECK-LABEL: absd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsabsdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast double %a to i64
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%and = and i64 %conv, 9223372036854775807
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @absv4f32(<4 x float> %a) {
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; CHECK-LABEL: absv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabssp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <4 x float> @absv4f32_wundef(<4 x float> %a) {
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; CHECK-LABEL: absv4f32_wundef:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabssp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <4 x float> @absv4f32_invalid(<4 x float> %a) {
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; CHECK-LABEL: absv4f32_invalid:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: xxswapd vs35, vs0
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; CHECK-NEXT: xxland vs34, vs34, vs35
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @absv2f64(<2 x double> %a) {
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; CHECK-LABEL: absv2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvabsdp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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define float @negf(float %a) {
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; CHECK-LABEL: negf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsnegdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast float %a to i32
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%and = xor i32 %conv, -2147483648
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @negd(double %a) {
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; CHECK-LABEL: negd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsnegdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast double %a to i64
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%and = xor i64 %conv, -9223372036854775808
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @negv4f32(<4 x float> %a) {
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; CHECK-LABEL: negv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnegsp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = xor <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @negv2d64(<2 x double> %a) {
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; CHECK-LABEL: negv2d64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnegdp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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define float @nabsf(float %a) {
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; CHECK-LABEL: nabsf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsnabsdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast float %a to i32
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%and = or i32 %conv, -2147483648
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%conv1 = bitcast i32 %and to float
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ret float %conv1
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}
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define double @nabsd(double %a) {
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; CHECK-LABEL: nabsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsnabsdp f1, f1
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast double %a to i64
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%and = or i64 %conv, -9223372036854775808
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%conv1 = bitcast i64 %and to double
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ret double %conv1
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}
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define <4 x float> @nabsv4f32(<4 x float> %a) {
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; CHECK-LABEL: nabsv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnabssp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <4 x float> %a to <4 x i32>
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%and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%conv1 = bitcast <4 x i32> %and to <4 x float>
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ret <4 x float> %conv1
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}
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define <2 x double> @nabsv2d64(<2 x double> %a) {
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; CHECK-LABEL: nabsv2d64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvnabsdp vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%conv = bitcast <2 x double> %a to <2 x i64>
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%and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
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%conv1 = bitcast <2 x i64> %and to <2 x double>
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ret <2 x double> %conv1
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}
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