llvm-project/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll
Simon Pilgrim b3a7ab6f1f [DAG] Don't allow implicit truncation in extract_element(bitcast(scalar_to_vector(X))) -> trunc(srl(X,C)) fold
Limits #117900 to only fold when scalar_to_vector doesn't perform implicit truncation, as the scaled shift calculation doesn't currently account for this - this can be addressed in a future update.

Fixes #121306
2024-12-30 16:08:35 +00:00

50 lines
1.8 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
define i8 @scalar_to_vector_half(ptr nocapture readonly %ad) {
; P9LE-LABEL: scalar_to_vector_half:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxsihzx v2, 0, r3
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vsplth v2, v2, 3
; P9LE-NEXT: vextubrx r3, r3, v2
; P9LE-NEXT: blr
;
; P9BE-LABEL: scalar_to_vector_half:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lxsihzx v2, 0, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vsplth v2, v2, 3
; P9BE-NEXT: vextublx r3, r3, v2
; P9BE-NEXT: blr
;
; P8LE-LABEL: scalar_to_vector_half:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lhz r3, 0(r3)
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: clrldi r3, r3, 56
; P8LE-NEXT: blr
;
; P8BE-LABEL: scalar_to_vector_half:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lhz r3, 0(r3)
; P8BE-NEXT: sldi r3, r3, 48
; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: mffprd r3, f0
; P8BE-NEXT: rldicl r3, r3, 8, 56
; P8BE-NEXT: blr
entry:
%0 = load <2 x i8>, ptr %ad, align 1
%1 = extractelement <2 x i8> %0, i32 0
ret i8 %1
}