ff9c5c334a
When generating code for functions that have `__builtin_frame_address` calls and `noinline` attribute, prologue was not emitted correctly leading to an assertion failure in PowerPC. The issue was due to improper insertion of prologue for a function that contain llvm `__builtin_frame_address`. Shrink-wrap pass computes the save and restore points of a function. Default points are the entry and exit points of the function. During shrink-wrapping the frame-pointer was not honored like the stack pointer and it was considered as a callee-saved register. This change will treat the FP similar to SP and will insert the prolog on top the instruction containing FP. --------- Co-authored-by: Tony Varghese <tony.varghese@ibm.com>
97 lines
3.6 KiB
LLVM
97 lines
3.6 KiB
LLVM
; Test file to verify the prologue and epilogue insertion point computation by the shrink-wrap pass
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC64
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC32-AIX
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC64-AIX
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define void @foo(ptr noundef readnone %parent_frame_pointer) {
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; POWERPC64-LABEL: foo
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; POWERPC64: # %bb.0:
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; POWERPC64: mflr [[REG1:[0-9]+]]
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; POWERPC64-NEXT: stdu 1, -32(1)
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; POWERPC64-NEXT: std [[REG1]], 48(1)
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; POWERPC64: cmpld [[REG2:[0-9]+]], 1
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; POWERPC64: # %bb.1:
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; POWERPC64-NEXT: addi 1, 1, 32
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; POWERPC64-NEXT: ld [[REG1]], 16(1)
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; POWERPC64-NEXT: mtlr [[REG1]]
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; POWERPC64-NEXT: blr
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; POWERPC32-AIX-LABEL: .foo:
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; POWERPC32-AIX: # %bb.0:
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; POWERPC32-AIX-NEXT: mflr [[REG1:[0-9]+]]
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; POWERPC32-AIX-NEXT: stwu 1, -64(1)
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; POWERPC32-AIX-NEXT: cmplw [[REG2:[0-9]+]], 1
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; POWERPC32-AIX: # %bb.1:
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; POWERPC32-AIX-NEXT: addi 1, 1, 64
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; POWERPC32-AIX-NEXT: lwz [[REG1]], 8(1)
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; POWERPC32-AIX-NEXT: mtlr [[REG1]]
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; POWERPC32-AIX-NEXT: blr
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; POWERPC64-AIX-LABEL: .foo:
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; POWERPC64-AIX: # %bb.0:
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; POWERPC64-AIX-NEXT: mflr [[REG1:[0-9]+]]
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; POWERPC64-AIX-NEXT: stdu 1, -112(1)
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; POWERPC64-AIX-NEXT: cmpld [[REG2:[0-9]+]], 1
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; POWERPC64-AIX: # %bb.1:
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; POWERPC64-AIX-NEXT: addi 1, 1, 112
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; POWERPC64-AIX-NEXT: ld [[REG1]], 16(1)
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; POWERPC64-AIX-NEXT: mtlr [[REG1]]
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; POWERPC64-AIX-NEXT: blr
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entry:
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%frameaddress = tail call ptr @llvm.frameaddress.p0(i32 0)
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%cmp = icmp ugt ptr %parent_frame_pointer, %frameaddress
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br i1 %cmp, label %cond.end, label %cond.false
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cond.false: ; preds = %entry
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tail call void @abort()
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unreachable
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cond.end: ; preds = %entry
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ret void
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}
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declare ptr @llvm.frameaddress.p0(i32 immarg)
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declare void @abort()
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define noundef i32 @main() {
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; POWERPC64-LABEL: main
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; POWERPC64: # %bb.0:
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; POWERPC64-NEXT: mflr [[REG1:[0-9]+]]
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; POWERPC64-NEXT: stdu 1, -32(1)
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; POWERPC64-NEXT: std [[REG1]], 48(1)
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; POWERPC64: mr [[REG2:[0-9]+]], 1
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; POWERPC64: addi 1, 1, 32
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; POWERPC64-NEXT: ld [[REG1]], 16(1)
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; POWERPC64-NEXT: mtlr [[REG1]]
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; POWERPC64-NEXT: blr
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; POWERPC32-AIX-LABEL: .main:
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; POWERPC32-AIX: # %bb.0:
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; POWERPC32-AIX-NEXT: mflr [[REG1:[0-9]+]]
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; POWERPC32-AIX-NEXT: stwu 1, -64(1)
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; POWERPC32-AIX-NEXT: mr [[REG2:[0-9]+]], 1
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; POWERPC32-AIX-NEXT: stw [[REG1]], 72(1)
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; POWERPC32-AIX: addi 1, 1, 64
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; POWERPC32-AIX-NEXT: lwz [[REG1]], 8(1)
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; POWERPC32-AIX-NEXT: mtlr [[REG1]]
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; POWERPC32-AIX-NEXT: blr
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; POWERPC64-AIX-LABEL: .main:
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; POWERPC64-AIX: # %bb.0:
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; POWERPC64-AIX-NEXT: mflr [[REG1:[0-9]+]]
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; POWERPC64-AIX-NEXT: stdu 1, -112(1)
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; POWERPC64-AIX-NEXT: mr [[REG2:[0-9]+]], 1
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; POWERPC64-AIX-NEXT: std [[REG1]], 128(1)
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; POWERPC64-AIX: addi 1, 1, 112
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; POWERPC64-AIX-NEXT: ld [[REG1]], 16(1)
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; POWERPC64-AIX-NEXT: mtlr [[REG1]]
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; POWERPC64-AIX-NEXT: blr
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entry:
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%frameaddress = tail call ptr @llvm.frameaddress.p0(i32 0)
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tail call void @foo(ptr noundef %frameaddress)
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ret i32 0
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}
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