88e2bb4092
This change seeks to add support for vendor flavoured SPIRV - more specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that carries some extra bits of information that are only usable by AMDGCN targets, forfeiting absolute genericity to obtain greater expressiveness for target features: - AMDGCN inline ASM is allowed/supported, under the assumption that the [SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc) extension is enabled/used - AMDGCN target specific builtins are allowed/supported, under the assumption that e.g. the `--spirv-allow-unknown-intrinsics` option is enabled when using the downstream translator - the featureset matches the union of AMDGCN targets' features - the datalayout string is overspecified to affix both the program address space and the alloca address space, the latter under the assumption that the [SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc) extension is enabled/used, case in which the extant SPIRV datalayout string would lead to pointers to function pointing to the private address space, which would be wrong. Existing AMDGCN tests are extended to cover this new target. It is currently dormant / will require some additional changes, but I thought I'd rather put it up for review to get feedback as early as possible. I will note that an alternative option is to place this under AMDGPU, but that seems slightly less natural, since this is still SPIRV, albeit relaxed in terms of preconditions & constrained in terms of postconditions, and only guaranteed to be usable on AMDGCN targets (it is still possible to obtain pristine portable SPIRV through usage of the flavoured target, though).
57 lines
1.7 KiB
C++
57 lines
1.7 KiB
C++
// RUN: %clang_cc1 -triple spirv64 -x hip -emit-llvm -fcuda-is-device \
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// RUN: -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \
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// RUN: -o - %s | FileCheck %s
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#define __device__ __attribute__((device))
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#define __shared__ __attribute__((shared))
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#define __constant__ __attribute__((constant))
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// CHECK: %struct.foo_t = type { i32, ptr addrspace(4) }
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// CHECK: @d ={{.*}} addrspace(1) externally_initialized global
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__device__ int d;
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// CHECK: @c ={{.*}} addrspace(1) externally_initialized global
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__constant__ int c;
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// CHECK: @s ={{.*}} addrspace(3) global
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__shared__ int s;
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// CHECK: @foo ={{.*}} addrspace(1) externally_initialized global %struct.foo_t
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__device__ struct foo_t {
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int i;
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int* pi;
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} foo;
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// Check literals are placed in address space 1 (CrossWorkGroup/__global).
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// CHECK: @.str ={{.*}} unnamed_addr addrspace(1) constant
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// CHECK: define{{.*}} spir_func noundef ptr addrspace(4) @_Z3barPi(ptr addrspace(4)
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__device__ int* bar(int *x) {
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return x;
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}
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// CHECK: define{{.*}} spir_func noundef ptr addrspace(4) @_Z5baz_dv()
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__device__ int* baz_d() {
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// CHECK: ret ptr addrspace(4) addrspacecast (ptr addrspace(1) @d to ptr addrspace(4)
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return &d;
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}
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// CHECK: define{{.*}} spir_func noundef ptr addrspace(4) @_Z5baz_cv()
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__device__ int* baz_c() {
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// CHECK: ret ptr addrspace(4) addrspacecast (ptr addrspace(1) @c to ptr addrspace(4)
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return &c;
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}
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// CHECK: define{{.*}} spir_func noundef ptr addrspace(4) @_Z5baz_sv()
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__device__ int* baz_s() {
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// CHECK: ret ptr addrspace(4) addrspacecast (ptr addrspace(3) @s to ptr addrspace(4)
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return &s;
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}
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// CHECK: define{{.*}} spir_func noundef ptr addrspace(4) @_Z3quzv()
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__device__ const char* quz() {
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return "abc";
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}
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