Hsiangkai Wang 9dbb6e1978

[mlir][spirv] Add target width to SPIR-V ABI (#88555) ...

There are execution modes need target width as their extra operands.
SignedZeroInfNanPreserve is one of them. This patch adds `target width`
as one of SPIR-V ABI attributes.

2024-04-15 17:59:17 +01:00

..

builtins-opencl.mlir

[mlir][spirv] Fix Physical32/Physical64 support for OpenCL

2023-02-27 06:22:59 +00:00

builtins-vulkan.mlir

[mlir][spirv] Fix Physical32/Physical64 support for OpenCL

2023-02-27 06:22:59 +00:00

entry-point.mlir

[mlir][spirv] Add target width to SPIR-V ABI (#88555)

2024-04-15 17:59:17 +01:00

gpu-to-spirv.mlir

…

load-store.mlir

[mlir][spirv] Improve folding of MemRef to SPIRV Lowering (#85433)

2024-03-21 08:49:27 -07:00

module-opencl.mlir

[mlir] Prepare convert-gpu-to-spirv for OpenCL support (#69941)

2023-11-05 18:56:53 -08:00

reductions.mlir

[mlir][gpu] Allow subgroup reductions over 1-d vector types (#76015)

2023-12-21 11:55:43 -05:00

shuffle.mlir

…

wmma-ops-to-spirv-khr-coop-matrix.mlir

[mlir][spirv] Drop support for SPV_NV_cooperative_matrix (#76782)

2024-01-08 17:57:52 -05:00