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llvm-project/llvm/test/CodeGen
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Vedant Kumar e0b60c6df2 [AArch64CollectLOH] Debug insts should not break LOH collection [14/14] 
Fix an issue where the presence of debug instructions could break
collection of linker optimization hints.
2020-04-22 17:03:41 -07:00
..
AArch64
[AArch64CollectLOH] Debug insts should not break LOH collection [14/14]
2020-04-22 17:03:41 -07:00
AMDGPU
[AMDGPU] Add 192-bit register classes
2020-04-22 13:10:37 +01:00
ARC
…
ARM
[ARM] Mark some tests as not safe for -debugify-and-strip-all, NFC
2020-04-22 17:03:39 -07:00
AVR
[AVR] Do not place functions in .progmem.data
2020-04-20 13:56:38 +02:00
BPF
BPF: fix a CORE optimization bug
2020-04-20 19:54:51 -07:00
Generic
[MachineDebugify] Insert synthetic DBG_VALUE instructions
2020-04-22 17:03:39 -07:00
Hexagon
[Pipeliner] Fix the bug in pragma that disables the pipeliner.
2020-04-10 12:52:16 -05:00
Inputs
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Lanai
…
Mips
[MIR] Add comments to INLINEASM immediate flag MachineOperands
2020-04-16 13:46:14 +02:00
MIR
[llvm][MIRVRegNamer] Avoid collisions across jump table indices.
2020-04-22 14:58:44 -04:00
MSP430
…
NVPTX
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
PowerPC
[PowerPC][Future] Initial support for PCRel addressing to get block address
2020-04-22 15:01:29 -05:00
RISCV
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[SystemZ] Bugfix in adjustSubwordCmp()
2020-04-15 12:58:39 +02:00
Thumb
[ARM] Don't shrink STM if it would cause an unknown base register store
2020-04-22 14:50:42 +01:00
Thumb2
[ARM] Replace arm vendor with none. NFC
2020-04-22 18:19:35 +01:00
VE
[VE] Update integer arithmetic instructions
2020-04-15 09:47:51 +02:00
WebAssembly
[WebAssembly] Add int32 DW_OP_WASM_location variant
2020-04-16 16:32:17 -07:00
WinCFGuard
…
WinEH
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X86
[NFC][llvm][X86] Adding missing -mtiple to X86 test.
2020-04-22 11:55:57 +01:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00