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llvm-project/llvm/lib/Target/AArch64
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Andrew Litteken 8d5024f7fe fix to outline cfi instruction when can be grouped in a tail call 
[MachineOutliner] fix test for excluding CFI and add test to include CFI in outlining

New test to check that we only outline CFI instruction if all CFI
Instructions in the function would be captured by the outlining

adding x86 tests analagous to AARCH64 cfi tests

Revision: https://reviews.llvm.org/D77852
2020-04-17 22:26:34 -07:00
..
AsmParser
[AArch64] Allow logical immediates to have all-1 in top bits
2020-04-06 09:56:04 -07:00
Disassembler
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
MCTargetDesc
MCObjectWriter.h - remove Endian.h/EndianStream.h/raw_ostream.h includes. NFC
2020-04-17 10:44:08 +01:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[AArch64][SVE] Add patterns for unpredicated load/store to frame-indices.
2020-01-22 14:32:27 +00:00
AArch64.h
[AArch64][SVE] Add a pass for SVE intrinsic optimisations
2020-04-14 10:41:49 +01:00
AArch64.td
[ARM] Add enhanced counter virtualization system registers
2020-04-05 15:18:35 +01:00
AArch64A53Fix835769.cpp
…
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
…
AArch64AsmPrinter.cpp
[MC] Add MCStreamer::emitInt{8,16,32,64}
2020-02-29 09:40:21 -08:00
AArch64BranchTargets.cpp
[AArch64] Fix BTI landing pad generation.
2020-02-13 10:44:34 +00:00
AArch64CallingConvention.cpp
…
AArch64CallingConvention.h
Add Windows Control Flow Guard checks (/guard:cf).
2019-10-28 15:19:39 +00:00
AArch64CallingConvention.td
[AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types
2019-12-12 09:49:22 +00:00
AArch64CallLowering.cpp
[AArch64][GlobalISel] CallLowering: Don't generate new copies each time we need
2020-04-09 17:08:56 -07:00
AArch64CallLowering.h
…
AArch64CleanupLocalDynamicTLSPass.cpp
[CallSiteInfo] Handle bundles when updating call site info
2020-02-27 13:57:06 +01:00
AArch64CollectLOH.cpp
…
AArch64Combine.td
[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS
2020-01-16 15:18:44 -08:00
AArch64CompressJumpTables.cpp
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
AArch64CondBrTuning.cpp
…
AArch64ConditionalCompares.cpp
Update spelling of {analyze,insert,remove}Branch in strings and comments
2020-01-21 10:15:38 -06:00
AArch64ConditionOptimizer.cpp
Update spelling of {analyze,insert,remove}Branch in strings and comments
2020-01-21 10:15:38 -06:00
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
…
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
AArch64FalkorHWPFFix.cpp
[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
2020-01-19 14:20:37 -08:00
AArch64FastISel.cpp
[Alignment][NFC] Transitionning more getMachineMemOperand call sites
2020-03-31 11:04:10 +00:00
AArch64FrameLowering.cpp
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
AArch64FrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
DAG: Use TargetConstant for FENCE operands
2020-01-02 17:16:10 -05:00
AArch64InstrFormats.td
[PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support
2020-03-26 09:17:20 +00:00
AArch64InstrInfo.cpp
fix to outline cfi instruction when can be grouped in a tail call
2020-04-17 22:26:34 -07:00
AArch64InstrInfo.h
CodeGen: Convert some TII hooks to use Register
2020-04-03 14:52:54 -04:00
AArch64InstrInfo.td
[ARM] Fix conditions for lowering to S[LR]I
2020-04-17 17:19:24 +01:00
AArch64InstructionSelector.cpp
[AArch64][GlobalISel] Constrain reg operands in selectBrJT
2020-04-02 20:34:11 -07:00
AArch64ISelDAGToDAG.cpp
[llvm][CodeGen] Addressing modes for SVE stN.
2020-04-17 20:35:35 +01:00
AArch64ISelLowering.cpp
[llvm][CodeGen] Addressing modes for SVE stN.
2020-04-17 20:35:35 +01:00
AArch64ISelLowering.h
[ARM] Fix conditions for lowering to S[LR]I
2020-04-17 17:19:24 +01:00
AArch64LegalizerInfo.cpp
[Alignment][NFC] Transitionning more getMachineMemOperand call sites
2020-03-31 11:04:10 +00:00
AArch64LegalizerInfo.h
GlobalISel: Add observer argument to legalizeIntrinsic
2020-01-29 18:33:45 -05:00
AArch64LoadStoreOptimizer.cpp
[AArch64][Fix] LdSt optimization generate premature stack-popping
2020-03-14 02:03:10 +00:00
AArch64MachineFunctionInfo.cpp
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64MachineFunctionInfo.h
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64MacroFusion.cpp
…
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PreLegalizerCombiner.cpp
[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS
2020-01-16 15:18:44 -08:00
AArch64PromoteConstant.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBankInfo.cpp
Reland "[AArch64] Fix data race on RegisterBank initialization."
2020-02-07 13:13:55 -08:00
AArch64RegisterBankInfo.h
GlobalISel: Add type argument to getRegBankFromRegClass
2020-01-03 16:25:10 -05:00
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
AArch64RegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
AArch64RegisterInfo.td
[AArch64] Add IR intrinsics for sq(r)dmulh_lane(q)
2020-01-29 13:25:23 +00:00
AArch64SchedA53.td
…
AArch64SchedA57.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedExynosM3.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedExynosM4.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedExynosM5.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedFalkor.td
…
AArch64SchedFalkorDetails.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedKryo.td
…
AArch64SchedKryoDetails.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedPredExynos.td
[AArch64] Add new scheduling predicates
2019-11-11 15:02:51 -06:00
AArch64SchedPredicates.td
[NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp
2019-11-23 19:11:31 +01:00
AArch64SchedThunderX2T99.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedThunderX.td
…
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp
[Alignment][NFC] Transitionning more getMachineMemOperand call sites
2020-03-31 11:04:10 +00:00
AArch64SelectionDAGInfo.h
…
AArch64SIMDInstrOpt.cpp
Make llvm::StringRef to std::string conversions explicit.
2020-01-28 23:25:25 +01:00
AArch64SpeculationHardening.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
AArch64StackOffset.h
Explicitly include <cassert> when using assert
2020-03-02 22:45:28 +01:00
AArch64StackTagging.cpp
[memtag] Plug in stack safety analysis.
2020-03-16 16:35:25 -07:00
AArch64StackTaggingPreRA.cpp
MTE: add more unchecked instructions.
2019-11-19 11:19:53 -08:00
AArch64StorePairSuppress.cpp
Add OffsetIsScalable to getMemOperandWithOffset
2020-02-18 15:53:29 +00:00
AArch64Subtarget.cpp
[AArch64] Add support for Fujitsu A64FX
2020-03-09 19:15:09 +09:00
AArch64Subtarget.h
[ARM] Add enhanced counter virtualization system registers
2020-04-05 15:18:35 +01:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add DestructiveBinaryImm SQSHLU patterns.
2020-04-16 13:48:08 -05:00
AArch64SystemOperands.td
[ARM] Add enhanced counter virtualization system registers
2020-04-05 15:18:35 +01:00
AArch64TargetMachine.cpp
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64TargetMachine.h
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64TargetObjectFile.cpp
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
2020-03-20 21:57:34 -07:00
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp
Clean up usages of asserting vector getters in Type
2020-04-09 16:43:29 -07:00
AArch64TargetTransformInfo.h
Clean up usages of asserting vector getters in Type
2020-04-09 16:43:29 -07:00
CMakeLists.txt
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
LLVMBuild.txt
Add Windows Control Flow Guard checks (/guard:cf).
2019-10-28 15:19:39 +00:00
SVEInstrFormats.td
[AArch64][SVE] Add DestructiveBinaryImm SQSHLU patterns.
2020-04-16 13:48:08 -05:00
SVEIntrinsicOpts.cpp
[AArch64][SVE] Add a pass for SVE intrinsic optimisations
2020-04-14 10:41:49 +01:00