79b29d6df7
I'm not sure why these were bothering to check the instruction profile, since those profiles should only be used with these instruction classes.
771 lines
23 KiB
TableGen
771 lines
23 KiB
TableGen
//===-- VOPInstructions.td - Vector Instruction Defintions ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// dummies for outer let
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class LetDummies {
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bit isCommutable;
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bit isConvertibleToThreeAddress;
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bit isMoveImm;
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bit isReMaterializable;
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bit isAsCheapAsAMove;
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bit VOPAsmPrefer32Bit;
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bit FPDPRounding;
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Predicate SubtargetPredicate;
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string Constraints;
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string DisableEncoding;
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list<SchedReadWrite> SchedRW;
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list<Register> Uses;
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list<Register> Defs;
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}
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class VOP <string opName> {
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string OpName = opName;
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}
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class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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let Uses = [EXEC];
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}
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class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,
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string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern>,
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VOP <opName>,
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SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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VOPProfile Pfl = P;
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string AsmOperands;
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}
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class VOP3Common <dag outs, dag ins, string asm = "",
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list<dag> pattern = [], bit HasMods = 0,
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bit VOP3Only = 0> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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// but standalone patterns are almost always preferred, so we need to adjust the
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// priority lower. The goal is to use a high number to reduce complexity to
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// zero (or less than zero).
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let AddedComplexity = -1000;
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let VOP3 = 1;
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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let AsmMatchConverter = !if(!eq(HasMods,1), "cvtVOP3", "");
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let isCodeGenOnly = 0;
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int Size = 8;
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// Because SGPRs may be allowed if there are multiple operands, we
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// need a post-isel hook to insert copies in order to avoid
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// violating constant bus requirements.
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let hasPostISelHook = 1;
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}
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class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
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bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> :
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VOP_Pseudo <opName, "_e64", P, P.Outs64,
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!if(isVop3OpSel,
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P.InsVOP3OpSel,
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!if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
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"", pattern> {
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let VOP3_OPSEL = isVop3OpSel;
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let IsPacked = P.IsPacked;
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let IsMAI = P.IsMAI;
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let AsmOperands = !if(isVop3OpSel,
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P.AsmVOP3OpSel,
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!if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
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let Size = 8;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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// Because SGPRs may be allowed if there are multiple operands, we
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// need a post-isel hook to insert copies in order to avoid
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// violating constant bus requirements.
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let hasPostISelHook = 1;
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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// but standalone patterns are almost always preferred, so we need to adjust the
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// priority lower. The goal is to use a high number to reduce complexity to
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// zero (or less than zero).
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let AddedComplexity = -1000;
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let VOP3 = 1;
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let VALU = 1;
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let FPClamp = P.HasFPClamp;
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let IntClamp = P.HasIntClamp;
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let ClampLo = P.HasClampLo;
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let ClampHi = P.HasClampHi;
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let Uses = [EXEC];
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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let AsmMatchConverter =
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!if(isVOP3P,
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"cvtVOP3P",
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!if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
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"cvtVOP3",
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""));
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}
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class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
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VOP3_Pseudo<opName, P, pattern, 1, 1> {
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let VOP3P = 1;
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}
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class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, EncodingFamily> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let UseNamedOperandTable = 1;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let OtherPredicates = ps.OtherPredicates;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let Uses = ps.Uses;
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let Defs = ps.Defs;
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VOPProfile Pfl = ps.Pfl;
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}
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// XXX - Is there any reason to distingusih this from regular VOP3
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// here?
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class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> :
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VOP3_Real<ps, EncodingFamily>;
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class VOP3a<VOPProfile P> : Enc64 {
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bits<4> src0_modifiers;
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bits<9> src0;
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bits<3> src1_modifiers;
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bits<9> src1;
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bits<3> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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bits<2> omod;
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let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
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let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0);
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let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{60-59} = !if(P.HasOMod, omod, 0);
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let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
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let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
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}
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class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> {
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let Inst{11} = !if(p.HasClamp, clamp{0}, 0);
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let Inst{25-17} = op;
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}
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class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> {
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let Inst{15} = !if(p.HasClamp, clamp{0}, 0);
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let Inst{25-16} = op;
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let Inst{31-26} = 0x35;
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}
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class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
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let Inst{25-16} = op;
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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}
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class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> {
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bits<8> vdst;
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let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
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}
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class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> {
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bits<8> vdst;
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let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
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}
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class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
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bits<8> vdst;
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let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
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}
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class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
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let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
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let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
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let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
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let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
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}
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class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
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let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
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let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0);
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let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0);
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let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0);
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}
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// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
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class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
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bits<2> attrchan;
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bits<6> attr;
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bits<1> high;
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let Inst{8} = 0; // No modifiers for src0
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let Inst{61} = 0;
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let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
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let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{37-32} = attr;
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let Inst{39-38} = attrchan;
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let Inst{40} = !if(P.HasHigh, high, 0);
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let Inst{49-41} = src0;
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}
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class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
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bits<6> attr;
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bits<2> attrchan;
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bits<1> high;
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let Inst{8} = 0;
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let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0);
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let Inst{37-32} = attr;
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let Inst{39-38} = attrchan;
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let Inst{40} = !if(p.HasHigh, high, 0);
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let Inst{49-41} = src0;
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let Inst{61} = 0;
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let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0);
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}
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class VOP3be <VOPProfile P> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<7> sdst;
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bits<2> omod;
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let Inst{7-0} = vdst;
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let Inst{14-8} = sdst;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{60-59} = !if(P.HasOMod, omod, 0);
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let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
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let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
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}
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class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
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bits<8> vdst;
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// neg, neg_hi, op_sel put in srcN_modifiers
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bits<4> src0_modifiers;
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bits<9> src0;
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bits<4> src1_modifiers;
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bits<9> src1;
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bits<4> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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let Inst{7-0} = vdst;
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let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
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let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1
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let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
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let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0)
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let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1)
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let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2)
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let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, 0); // op_sel_hi(2)
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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let Inst{25-16} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, 0); // op_sel_hi(0)
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let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, 0); // op_sel_hi(1)
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let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo)
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let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo)
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let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo)
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}
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class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 {
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bits<8> vdst;
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bits<10> src0;
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bits<10> src1;
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bits<9> src2;
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bits<3> blgp;
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bits<3> cbsz;
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bits<4> abid;
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bits<1> clamp;
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let Inst{7-0} = vdst;
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let Inst{10-8} = !if(P.HasSrc1, cbsz, 0);
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let Inst{14-11} = !if(P.HasSrc1, abid, 0);
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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let Inst{25-16} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0)
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let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1)
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let Inst{63-61} = !if(P.HasSrc1, blgp, 0);
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}
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class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> {
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let Inst{31-26} = 0x33; //encoding
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}
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class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {
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let Inst{25-17} = op;
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}
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class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> {
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bits<1> clamp;
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let Inst{15} = !if(p.HasClamp, clamp{0}, 0);
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let Inst{25-16} = op;
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let Inst{31-26} = 0x35;
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}
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class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
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bits<1> clamp;
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let Inst{25-16} = op;
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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}
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def SDWA {
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// sdwa_sel
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int BYTE_0 = 0;
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int BYTE_1 = 1;
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int BYTE_2 = 2;
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int BYTE_3 = 3;
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int WORD_0 = 4;
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int WORD_1 = 5;
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int DWORD = 6;
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// dst_unused
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int UNUSED_PAD = 0;
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int UNUSED_SEXT = 1;
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int UNUSED_PRESERVE = 2;
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}
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class VOP_SDWAe<VOPProfile P> : Enc64 {
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bits<8> src0;
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bits<3> src0_sel;
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bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
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bits<3> src1_sel;
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bits<2> src1_modifiers;
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bits<3> dst_sel;
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bits<2> dst_unused;
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bits<1> clamp;
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0);
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let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0);
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let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
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let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
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let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
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let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
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let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
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let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
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let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
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}
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// GFX9 adds two features to SDWA:
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// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
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// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather
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// than VGPRs (at most 1 can be an SGPR);
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// b. OMOD is the standard output modifier (result *2, *4, /2)
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// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
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// replaces OMOD and the dest fields with SD and SDST (SGPR destination)
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// field.
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// a. When SD=1, the SDST is used as the destination for the compare result;
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// b. When SD=0, VCC is used.
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//
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// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
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// gfx9 SDWA basic encoding
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class VOP_SDWA9e<VOPProfile P> : Enc64 {
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bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
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bits<3> src0_sel;
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bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
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bits<3> src1_sel;
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bits<2> src1_modifiers;
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bits<1> src1_sgpr;
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
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let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
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let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
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let Inst{55} = !if(P.HasSrc0, src0{8}, 0);
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let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
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let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
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let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
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let Inst{63} = 0; // src1_sgpr - should be specified in subclass
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}
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// gfx9 SDWA-A
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class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> {
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bits<3> dst_sel;
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bits<2> dst_unused;
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bits<1> clamp;
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bits<2> omod;
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let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0);
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let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0);
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let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
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let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
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}
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// gfx9 SDWA-B
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class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> {
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bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
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let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
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let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
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}
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class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
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InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>,
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VOP <opName>,
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SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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string AsmOperands = P.AsmSDWA;
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string AsmOperands9 = P.AsmSDWA9;
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let Size = 8;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let VALU = 1;
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let SDWA = 1;
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let Uses = [EXEC];
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let SubtargetPredicate = HasSDWA;
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let AssemblerPredicate = HasSDWA;
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let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
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AMDGPUAsmVariants.Disable);
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let DecoderNamespace = "SDWA";
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VOPProfile Pfl = P;
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}
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class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let Defs = ps.Defs;
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let Uses = ps.Uses;
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let SchedRW = ps.SchedRW;
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let hasSideEffects = ps.hasSideEffects;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// Copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AssemblerPredicate = ps.AssemblerPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let DecoderNamespace = ps.DecoderNamespace;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let Defs = ps.Defs;
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let Uses = ps.Uses;
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let SchedRW = ps.SchedRW;
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let hasSideEffects = ps.hasSideEffects;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let SubtargetPredicate = HasSDWA9;
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let AssemblerPredicate = HasSDWA9;
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let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
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AMDGPUAsmVariants.Disable);
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let DecoderNamespace = "SDWA9";
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// Copy relevant pseudo op flags
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let AsmMatchConverter = ps.AsmMatchConverter;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
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Base_VOP_SDWA9_Real <ps >,
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SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
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class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
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let SubtargetPredicate = HasSDWA10;
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let AssemblerPredicate = HasSDWA10;
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let DecoderNamespace = "SDWA10";
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}
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class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> :
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Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>;
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class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 {
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bits<2> src0_modifiers;
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bits<8> src0;
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bits<2> src1_modifiers;
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bits<9> dpp_ctrl;
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bits<1> bound_ctrl;
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bits<4> bank_mask;
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bits<4> row_mask;
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bit fi;
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{48-40} = dpp_ctrl;
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let Inst{50} = !if(IsDPP16, fi, ?);
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let Inst{51} = bound_ctrl;
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let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
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let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
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let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
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let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
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let Inst{59-56} = bank_mask;
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let Inst{63-60} = row_mask;
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}
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class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
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InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>,
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VOP <OpName>,
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SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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let DPP = 1;
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let Size = 8;
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let Uses = [EXEC];
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let isConvergent = 1;
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string Mnemonic = OpName;
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string AsmOperands = P.AsmDPP;
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let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
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let SubtargetPredicate = HasDPP;
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let AssemblerPredicate = HasDPP;
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let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
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AMDGPUAsmVariants.Disable);
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let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
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let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
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let DecoderNamespace = "DPP";
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VOPProfile Pfl = P;
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}
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class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, EncodingFamily> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let Defs = ps.Defs;
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let Uses = ps.Uses;
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let SchedRW = ps.SchedRW;
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let hasSideEffects = ps.hasSideEffects;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// Copy relevant pseudo op flags
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let isConvergent = ps.isConvergent;
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AssemblerPredicate = ps.AssemblerPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let DecoderNamespace = ps.DecoderNamespace;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
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dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP),
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string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> :
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InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>,
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VOP_DPPe<P, IsDPP16> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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let DPP = 1;
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let Size = 8;
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let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
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let SubtargetPredicate = HasDPP;
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let AssemblerPredicate = HasDPP;
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let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
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AMDGPUAsmVariants.Disable);
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let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
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let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
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let DecoderNamespace = "DPP";
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}
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|
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class VOP_DPP8e<VOPProfile P> : Enc64 {
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bits<8> src0;
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bits<24> dpp8;
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bits<9> fi;
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|
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{63-40} = dpp8{23-0};
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|
}
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|
|
class VOP_DPP8<string OpName, VOPProfile P> :
|
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InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>,
|
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VOP_DPP8e<P> {
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|
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let mayLoad = 0;
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|
let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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|
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let VALU = 1;
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let DPP = 1;
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let Size = 8;
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|
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let AsmMatchConverter = "cvtDPP8";
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let SubtargetPredicate = HasDPP8;
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let AssemblerPredicate = HasDPP8;
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let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
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AMDGPUAsmVariants.Disable);
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let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
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let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
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}
|
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|
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def DPP8Mode {
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int FI_0 = 0xE9;
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int FI_1 = 0xEA;
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}
|
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|
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class getNumNodeArgs<SDPatternOperator Op> {
|
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SDNode N = !cast<SDNode>(Op);
|
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SDTypeProfile TP = N.TypeProfile;
|
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int ret = TP.NumOperands;
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}
|
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|
|
|
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class getDivergentFrag<SDPatternOperator Op> {
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|
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int NumSrcArgs = getNumNodeArgs<Op>.ret;
|
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PatFrag ret = PatFrag <
|
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!if(!eq(NumSrcArgs, 1),
|
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(ops node:$src0),
|
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!if(!eq(NumSrcArgs, 2),
|
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(ops node:$src0, node:$src1),
|
|
(ops node:$src0, node:$src1, node:$src2))),
|
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!if(!eq(NumSrcArgs, 1),
|
|
(Op $src0),
|
|
!if(!eq(NumSrcArgs, 2),
|
|
(Op $src0, $src1),
|
|
(Op $src0, $src1, $src2))),
|
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[{ return N->isDivergent(); }]
|
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>;
|
|
}
|
|
|
|
class VOPPatGen<SDPatternOperator Op, VOPProfile P> {
|
|
|
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PatFrag Operator = getDivergentFrag < Op >.ret;
|
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|
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dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator,
|
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!subst(P.Src0RC32, P.Src0VT,
|
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!subst(P.Src1RC32, P.Src1VT, tmp))));
|
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|
|
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dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set,
|
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!subst(P.DstRC, P.DstVT, tmp)));
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|
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list<dag> ret = [!con(Outs, (set Ins))];
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}
|
|
|
|
class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> {
|
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list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []);
|
|
}
|
|
|
|
class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> {
|
|
SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern),
|
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!if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op);
|
|
}
|
|
|
|
include "VOPCInstructions.td"
|
|
include "VOP1Instructions.td"
|
|
include "VOP2Instructions.td"
|
|
include "VOP3Instructions.td"
|
|
include "VOP3PInstructions.td"
|