a26bd4ec16
For context, the proposed RISC-V bit manipulation extension has a subset of instructions which require one of two SubtargetFeatures to be enabled, 'zbb' or 'zbp', and there is no defined feature which both of these can imply to use as a constraint either (see comments in D65649). AssemblerPredicates allow multiple SubtargetFeatures to be declared in the "AssemblerCondString" field, separated by commas, and this means that the two features must both be enabled. There is no equivalent to say that _either_ feature X or feature Y must be enabled, short of creating a dummy SubtargetFeature for this purpose and having features X and Y imply the new feature. To solve the case where X or Y is needed without adding a new feature, and to better match a typical TableGen style, this replaces the existing "AssemblerCondString" with a dag "AssemblerCondDag" which represents the same information. Two operators are defined for use with AssemblerCondDag, "all_of", which matches the current behaviour, and "any_of", which adds the new proposed ORing features functionality. This was originally proposed in the RFC at http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html Changes to all current backends are mechanical to support the replaced functionality, and are NFCI. At this stage, it is illegal to combine features with ands and ors in a single AssemblerCondDag. I suspect this case is sufficiently rare that adding more complex changes to support it are unnecessary. Differential Revision: https://reviews.llvm.org/D74338
346 lines
14 KiB
TableGen
346 lines
14 KiB
TableGen
// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly Instruction definitions.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def IsPIC : Predicate<"TM.isPositionIndependent()">;
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def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
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def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
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def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
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def HasSIMD128 :
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Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<(all_of FeatureSIMD128), "simd128">;
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def HasUnimplementedSIMD128 :
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Predicate<"Subtarget->hasUnimplementedSIMD128()">,
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AssemblerPredicate<(all_of FeatureUnimplementedSIMD128), "unimplemented-simd128">;
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def HasAtomics :
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Predicate<"Subtarget->hasAtomics()">,
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AssemblerPredicate<(all_of FeatureAtomics), "atomics">;
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def HasMultivalue :
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Predicate<"Subtarget->hasMultivalue()">,
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AssemblerPredicate<(all_of FeatureMultivalue), "multivalue">;
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def HasNontrappingFPToInt :
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Predicate<"Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<(all_of FeatureNontrappingFPToInt), "nontrapping-fptoint">;
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def NotHasNontrappingFPToInt :
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Predicate<"!Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<(all_of (not FeatureNontrappingFPToInt)), "nontrapping-fptoint">;
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def HasSignExt :
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Predicate<"Subtarget->hasSignExt()">,
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AssemblerPredicate<(all_of FeatureSignExt), "sign-ext">;
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def HasTailCall :
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Predicate<"Subtarget->hasTailCall()">,
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AssemblerPredicate<(all_of FeatureTailCall), "tail-call">;
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def HasExceptionHandling :
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Predicate<"Subtarget->hasExceptionHandling()">,
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AssemblerPredicate<(all_of FeatureExceptionHandling), "exception-handling">;
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def HasBulkMemory :
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Predicate<"Subtarget->hasBulkMemory()">,
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AssemblerPredicate<(all_of FeatureBulkMemory), "bulk-memory">;
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def HasReferenceTypes :
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Predicate<"Subtarget->hasReferenceTypes()">,
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AssemblerPredicate<(all_of FeatureReferenceTypes), "reference-types">;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Node Types.
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//===----------------------------------------------------------------------===//
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def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
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SDTCisVT<1, iPTR>]>;
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def SDT_WebAssemblyCallSeqEnd :
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SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
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def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
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def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
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def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def WebAssemblycallseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def WebAssemblycallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
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SDT_WebAssemblyBrTable,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
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SDT_WebAssemblyArgument>;
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def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
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SDT_WebAssemblyReturn,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
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SDT_WebAssemblyWrapper>;
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def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC",
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SDT_WebAssemblyWrapperPIC>;
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def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow,
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[SDNPHasChain, SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific Operands.
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//===----------------------------------------------------------------------===//
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// Default Operand has AsmOperandClass "Imm" which is for integers (and
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// symbols), so specialize one for floats:
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def FPImmAsmOperand : AsmOperandClass {
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let Name = "FPImm";
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let PredicateMethod = "isFPImm";
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}
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class FPOperand<ValueType ty> : Operand<ty> {
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AsmOperandClass ParserMatchClass = FPImmAsmOperand;
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}
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let OperandNamespace = "WebAssembly" in {
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let OperandType = "OPERAND_BASIC_BLOCK" in
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def bb_op : Operand<OtherVT>;
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let OperandType = "OPERAND_LOCAL" in
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def local_op : Operand<i32>;
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let OperandType = "OPERAND_GLOBAL" in
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def global_op : Operand<i32>;
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let OperandType = "OPERAND_I32IMM" in
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def i32imm_op : Operand<i32>;
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let OperandType = "OPERAND_I64IMM" in
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def i64imm_op : Operand<i64>;
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let OperandType = "OPERAND_F32IMM" in
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def f32imm_op : FPOperand<f32>;
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let OperandType = "OPERAND_F64IMM" in
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def f64imm_op : FPOperand<f64>;
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let OperandType = "OPERAND_VEC_I8IMM" in
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def vec_i8imm_op : Operand<i32>;
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let OperandType = "OPERAND_VEC_I16IMM" in
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def vec_i16imm_op : Operand<i32>;
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let OperandType = "OPERAND_VEC_I32IMM" in
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def vec_i32imm_op : Operand<i32>;
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let OperandType = "OPERAND_VEC_I64IMM" in
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def vec_i64imm_op : Operand<i64>;
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let OperandType = "OPERAND_FUNCTION32" in
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def function32_op : Operand<i32>;
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let OperandType = "OPERAND_OFFSET32" in
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def offset32_op : Operand<i32>;
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let OperandType = "OPERAND_P2ALIGN" in {
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def P2Align : Operand<i32> {
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let PrintMethod = "printWebAssemblyP2AlignOperand";
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}
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let OperandType = "OPERAND_EVENT" in
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def event_op : Operand<i32>;
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} // OperandType = "OPERAND_P2ALIGN"
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let OperandType = "OPERAND_SIGNATURE" in
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def Signature : Operand<i32> {
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let PrintMethod = "printWebAssemblySignatureOperand";
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}
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let OperandType = "OPERAND_TYPEINDEX" in
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def TypeIndex : Operand<i32>;
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} // OperandNamespace = "WebAssembly"
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//===----------------------------------------------------------------------===//
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// WebAssembly Register to Stack instruction mapping
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//===----------------------------------------------------------------------===//
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class StackRel;
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def getStackOpcode : InstrMapping {
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let FilterClass = "StackRel";
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let RowFields = ["BaseName"];
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let ColFields = ["StackBased"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format Definitions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Additional instructions.
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//===----------------------------------------------------------------------===//
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multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
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let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>,
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Uses = [ARGUMENTS] in
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defm ARGUMENT_#vt :
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I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
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[(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
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}
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defm "": ARGUMENT<I32, i32>;
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defm "": ARGUMENT<I64, i64>;
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defm "": ARGUMENT<F32, f32>;
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defm "": ARGUMENT<F64, f64>;
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defm "": ARGUMENT<EXNREF, exnref>;
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// local.get and local.set are not generated by instruction selection; they
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// are implied by virtual register uses and defs.
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multiclass LOCAL<WebAssemblyRegClass vt> {
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let hasSideEffects = 0 in {
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// COPY is not an actual instruction in wasm, but since we allow local.get and
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// local.set to be implicit during most of codegen, we can have a COPY which
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// is actually a no-op because all the work is done in the implied local.get
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// and local.set. COPYs are eliminated (and replaced with
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// local.get/local.set) in the ExplicitLocals pass.
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let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
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defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [],
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"local.copy\t$res, $src", "local.copy">;
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// TEE is similar to COPY, but writes two copies of its result. Typically
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// this would be used to stackify one result and write the other result to a
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// local.
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let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
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defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [],
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"local.tee\t$res, $also, $src", "local.tee">;
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// This is the actual local.get instruction in wasm. These are made explicit
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// by the ExplicitLocals pass. It has mayLoad because it reads from a wasm
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// local, which is a side effect not otherwise modeled in LLVM.
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let mayLoad = 1, isAsCheapAsAMove = 1 in
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defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local),
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(outs), (ins local_op:$local), [],
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"local.get\t$res, $local", "local.get\t$local", 0x20>;
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// This is the actual local.set instruction in wasm. These are made explicit
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// by the ExplicitLocals pass. It has mayStore because it writes to a wasm
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// local, which is a side effect not otherwise modeled in LLVM.
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let mayStore = 1, isAsCheapAsAMove = 1 in
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defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src),
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(outs), (ins local_op:$local), [],
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"local.set\t$local, $src", "local.set\t$local", 0x21>;
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// This is the actual local.tee instruction in wasm. TEEs are turned into
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// LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason
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// as LOCAL_SET.
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let mayStore = 1, isAsCheapAsAMove = 1 in
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defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src),
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(outs), (ins local_op:$local), [],
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"local.tee\t$res, $local, $src", "local.tee\t$local",
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0x22>;
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// Unused values must be dropped in some contexts.
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defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [],
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"drop\t$src", "drop", 0x1a>;
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let mayLoad = 1 in
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defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local),
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(outs), (ins global_op:$local), [],
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"global.get\t$res, $local", "global.get\t$local",
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0x23>;
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let mayStore = 1 in
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defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src),
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(outs), (ins global_op:$local), [],
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"global.set\t$local, $src", "global.set\t$local",
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0x24>;
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} // hasSideEffects = 0
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}
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defm "" : LOCAL<I32>;
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defm "" : LOCAL<I64>;
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defm "" : LOCAL<F32>;
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defm "" : LOCAL<F64>;
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defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
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defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>;
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let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
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defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
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(outs), (ins i32imm_op:$imm),
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[(set I32:$res, imm:$imm)],
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"i32.const\t$res, $imm", "i32.const\t$imm", 0x41>;
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defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
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(outs), (ins i64imm_op:$imm),
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[(set I64:$res, imm:$imm)],
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"i64.const\t$res, $imm", "i64.const\t$imm", 0x42>;
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defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
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(outs), (ins f32imm_op:$imm),
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[(set F32:$res, fpimm:$imm)],
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"f32.const\t$res, $imm", "f32.const\t$imm", 0x43>;
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defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
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(outs), (ins f64imm_op:$imm),
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[(set F64:$res, fpimm:$imm)],
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"f64.const\t$res, $imm", "f64.const\t$imm", 0x44>;
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} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
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def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
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(CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>;
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def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
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(GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
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def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)),
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(CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
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def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
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(GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>;
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def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
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(CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>;
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def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>;
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def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>;
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//===----------------------------------------------------------------------===//
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// Additional sets of instructions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrMemory.td"
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include "WebAssemblyInstrCall.td"
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include "WebAssemblyInstrControl.td"
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include "WebAssemblyInstrInteger.td"
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include "WebAssemblyInstrConv.td"
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include "WebAssemblyInstrFloat.td"
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include "WebAssemblyInstrAtomics.td"
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include "WebAssemblyInstrSIMD.td"
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include "WebAssemblyInstrRef.td"
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include "WebAssemblyInstrBulkMemory.td"
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