e53a9d96e6
The current implementation of skip insertion (SIInsertSkip) makes it a mandatory pass required for correctness. Initially, the idea was to have an optional pass. This patch inserts the s_cbranch_execz upfront during SILowerControlFlow to skip over the sections of code when no lanes are active. Later, SIRemoveShortExecBranches removes the skips for short branches, unless there is a sideeffect and the skip branch is really necessary. This new pass will replace the handling of skip insertion in the existing SIInsertSkip Pass. Differential revision: https://reviews.llvm.org/D68092
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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; GCN-LABEL: {{^}}convergent_inlineasm:
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; GCN: %bb.0:
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; GCN: v_cmp_ne_u32_e64
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; GCN: s_cbranch_execz
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; GCN: ; %bb.{{[0-9]+}}:
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define amdgpu_kernel void @convergent_inlineasm(i64 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 1) #1
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%tmp2 = icmp eq i32 %tmp, 8
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br i1 %tmp2, label %bb3, label %bb5
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bb3: ; preds = %bb
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%tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp
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store i64 %tmp1, i64 addrspace(1)* %arg, align 8
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br label %bb5
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bb5: ; preds = %bb3, %bb
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ret void
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}
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; GCN-LABEL: {{^}}nonconvergent_inlineasm:
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; GCN: s_cbranch_execz
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; GCN: ; %bb.{{[0-9]+}}:
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; GCN: v_cmp_ne_u32_e64
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; GCN: BB{{[0-9]+_[0-9]+}}:
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define amdgpu_kernel void @nonconvergent_inlineasm(i64 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 1)
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%tmp2 = icmp eq i32 %tmp, 8
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br i1 %tmp2, label %bb3, label %bb5
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bb3: ; preds = %bb
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%tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp
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store i64 %tmp1, i64 addrspace(1)* %arg, align 8
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br label %bb5
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bb5: ; preds = %bb3, %bb
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { convergent nounwind readnone }
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