43830790d7
Summary: pickNodeBidirectional tried to compare the best top candidate and the best bottom candidate by examining TopCand.Reason and BotCand.Reason. This is unsound because, after calling pickNodeFromQueue, Cand.Reason does not reflect the most important reason why Cand was chosen. Rather it reflects the most recent reason why it beat some other potential candidate, which could have been for some low priority tie breaker reason. I have seen this cause problems where TopCand is a good candidate, but because TopCand.Reason is ORDER (which is very low priority) it is repeatedly ignored in favour of a mediocre BotCand. This is not how bidirectional scheduling is supposed to work. To fix this I changed the code to always compare TopCand and BotCand directly, like the generic implementation of pickNodeBidirectional does. This removes some uncommented AMDGPU-specific logic; if this logic turns out to be important then perhaps it could be moved into an override of tryCandidate instead. Graphics shader benchmarking on gfx10 shows a lot more positive than negative effects from this change. Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68338
53 lines
2.3 KiB
YAML
53 lines
2.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=machine-scheduler -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# handleMove was called for the BUNDLE pseudo-instruction, but
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# considered it to be an instruction in the bundle. Make sure it
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# doesn't assert when the whole bundle is moved.
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---
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name: handleMove_bundle
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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memoryBound: false
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waveLimiter: false
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body: |
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bb.0:
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liveins: $sgpr4_sgpr5
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; GCN-LABEL: name: handleMove_bundle
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; GCN: liveins: $sgpr4_sgpr5
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; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GCN: $vcc_hi = IMPLICIT_DEF
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; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
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; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
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; GCN: $m0 = S_MOV_B32 0
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; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
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; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
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; GCN: DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
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; GCN: S_WAITCNT 0
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; GCN: }
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; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
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; GCN: S_ENDPGM 0
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$vcc_hi = IMPLICIT_DEF
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%2:sgpr_64 = COPY $sgpr4_sgpr5
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%5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %2, 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
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%6:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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DS_WRITE_B32_gfx9 %7, %6, 0, 0, implicit $exec :: (store 4, addrspace 3)
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$m0 = S_MOV_B32 0
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$vgpr0 = COPY %5
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BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
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DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
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S_WAITCNT 0
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}
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%8:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
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DS_WRITE_B32_gfx9 %7, %8, 0, 0, implicit $exec :: (store 4, addrspace 3)
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S_ENDPGM 0
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...
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