43830790d7
Summary: pickNodeBidirectional tried to compare the best top candidate and the best bottom candidate by examining TopCand.Reason and BotCand.Reason. This is unsound because, after calling pickNodeFromQueue, Cand.Reason does not reflect the most important reason why Cand was chosen. Rather it reflects the most recent reason why it beat some other potential candidate, which could have been for some low priority tie breaker reason. I have seen this cause problems where TopCand is a good candidate, but because TopCand.Reason is ORDER (which is very low priority) it is repeatedly ignored in favour of a mediocre BotCand. This is not how bidirectional scheduling is supposed to work. To fix this I changed the code to always compare TopCand and BotCand directly, like the generic implementation of pickNodeBidirectional does. This removes some uncommented AMDGPU-specific logic; if this logic turns out to be important then perhaps it could be moved into an override of tryCandidate instead. Graphics shader benchmarking on gfx10 shows a lot more positive than negative effects from this change. Reviewers: arsenm, tstellar, rampitec, kzhuravl, vpykhtin, dstuttard, tpr, atrick, MatzeB Subscribers: jvesely, wdng, nhaehnle, yaxunl, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68338
176 lines
5.8 KiB
LLVM
176 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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; ===================================================================================
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; V_XOR3_B32
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; ===================================================================================
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define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) {
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; GFX9-LABEL: xor3:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = xor i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
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; GFX9-LABEL: xor3_vgpr_b:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
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; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_vgpr_b:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, s2, v0, s3
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = xor i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
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; GFX9-LABEL: xor3_vgpr_all2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_vgpr_all2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v0
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %b, %c
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%result = xor i32 %a, %x
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
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; GFX9-LABEL: xor3_vgpr_bc:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_vgpr_bc:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = xor i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) {
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; GFX9-LABEL: xor3_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_xor_b32_e32 v0, 16, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 16
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = xor i32 %a, %b
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%result = xor i32 %x, 16
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
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; GFX9-LABEL: xor3_multiuse_outer:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_multiuse_outer:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
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; GFX10-NEXT: ; return to shader part epilog
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%inner = xor i32 %a, %b
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%outer = xor i32 %inner, %c
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%x1 = mul i32 %outer, %x
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%r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
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%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
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%bc = bitcast <2 x i32> %r0 to <2 x float>
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ret <2 x float> %bc
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}
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define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
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; GFX9-LABEL: xor3_multiuse_inner:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_multiuse_inner:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2
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; GFX10-NEXT: ; return to shader part epilog
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%inner = xor i32 %a, %b
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%outer = xor i32 %inner, %c
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%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
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%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
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%bc = bitcast <2 x i32> %r0 to <2 x float>
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ret <2 x float> %bc
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}
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; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here,
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; but we don't.
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define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
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; GFX9-LABEL: xor3_uniform_vgpr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000
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; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0
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; GFX9-NEXT: v_add_f32_e32 v2, s4, v2
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: xor3_uniform_vgpr:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
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; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
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; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2
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; GFX10-NEXT: ; return to shader part epilog
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%a1 = fadd float %a, 1.0
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%b2 = fadd float %b, 2.0
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%c3 = fadd float %c, 3.0
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%bc.a = bitcast float %a1 to i32
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%bc.b = bitcast float %b2 to i32
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%bc.c = bitcast float %c3 to i32
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%x = xor i32 %bc.a, %bc.b
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%result = xor i32 %x, %bc.c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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