d6351340bb
Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
100 lines
2.9 KiB
LLVM
100 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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; CHECK-LABEL: ret_void_args_i8
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define void @ret_void_args_i8(i8 %a) {
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; CHECK: sts 4, r24
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store volatile i8 %a, i8* inttoptr (i64 4 to i8*)
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ret void
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}
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; CHECK-LABEL: ret_void_args_i8_i32
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define void @ret_void_args_i8_i32(i8 %a, i32 %b) {
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; CHECK: sts 4, r24
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store volatile i8 %a, i8* inttoptr (i64 4 to i8*)
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; CHECK-NEXT: sts 8, r23
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; CHECK-NEXT: sts 7, r22
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; CHECK-NEXT: sts 6, r21
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; CHECK-NEXT: sts 5, r20
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store volatile i32 %b, i32* inttoptr (i64 5 to i32*)
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ret void
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}
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; CHECK-LABEL: ret_void_args_i8_i8_i8_i8
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define void @ret_void_args_i8_i8_i8_i8(i8 %a, i8 %b, i8 %c, i8 %d) {
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; CHECK: sts 4, r24
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store volatile i8 %a, i8* inttoptr (i64 4 to i8*)
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; CHECK-NEXT: sts 5, r22
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store volatile i8 %b, i8* inttoptr (i64 5 to i8*)
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; CHECK-NEXT: sts 6, r20
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store volatile i8 %c, i8* inttoptr (i64 6 to i8*)
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; CHECK-NEXT: sts 7, r18
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store volatile i8 %d, i8* inttoptr (i64 7 to i8*)
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ret void
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}
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; CHECK-LABEL: ret_void_args_i32_16_i8
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define void @ret_void_args_i32_16_i8(i32 %a, i16 %b, i8 %c) {
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; CHECK: sts 7, r25
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; CHECK-NEXT: sts 6, r24
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; CHECK-NEXT: sts 5, r23
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; CHECK-NEXT: sts 4, r22
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store volatile i32 %a, i32* inttoptr (i64 4 to i32*)
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; CHECK-NEXT: sts 5, r21
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; CHECK-NEXT: sts 4, r20
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store volatile i16 %b, i16* inttoptr (i64 4 to i16*)
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; CHECK-NEXT: sts 4, r18
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store volatile i8 %c, i8* inttoptr (i64 4 to i8*)
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ret void
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}
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; CHECK-LABEL: ret_void_args_i64
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define void @ret_void_args_i64(i64 %a) {
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; CHECK: sts 11, r25
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; CHECK-NEXT: sts 10, r24
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; CHECK-NEXT: sts 9, r23
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; CHECK-NEXT: sts 8, r22
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; CHECK-NEXT: sts 7, r21
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; CHECK-NEXT: sts 6, r20
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; CHECK-NEXT: sts 5, r19
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; CHECK-NEXT: sts 4, r18
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store volatile i64 %a, i64* inttoptr (i64 4 to i64*)
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ret void
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}
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; CHECK-LABEL: ret_void_args_i64_i64
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define void @ret_void_args_i64_i64(i64 %a, i64 %b) {
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; CHECK-DAG: sts 11, r25
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; CHECK-DAG: sts 10, r24
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; CHECK-DAG: sts 9, r23
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; CHECK-DAG: sts 8, r22
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; CHECK-DAG: sts 7, r21
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; CHECK-DAG: sts 6, r20
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; CHECK-DAG: sts 5, r19
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; CHECK-DAG: sts 4, r18
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store volatile i64 %a, i64* inttoptr (i64 4 to i64*)
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; CHECK-DAG: sts 11, r17
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; CHECK-DAG: sts 10, r16
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; CHECK-DAG: sts 9, r15
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; CHECK-DAG: sts 8, r14
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; CHECK-DAG: sts 7, r13
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; CHECK-DAG: sts 6, r12
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; CHECK-DAG: sts 5, r11
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; CHECK-DAG: sts 4, r10
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store volatile i64 %b, i64* inttoptr (i64 4 to i64*)
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ret void
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}
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; This is exactly enough to hit the limit of what can be passed
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; completely in registers.
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; CHECK-LABEL: ret_void_args_i64_i64_i16
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define void @ret_void_args_i64_i64_i16(i64 %a, i64 %b, i16 %c) {
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; CHECK: sts 5, r9
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; CHECK-NEXT: sts 4, r8
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store volatile i16 %c, i16* inttoptr (i64 4 to i16*)
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ret void
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}
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