b413e5c309
Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp. These will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments. dcbfl ra, rb -> dcbf ra, rb, 1 dcbflp, ra, rb -> dcbf ra, rb, 3 Differential Revision: https://reviews.llvm.org/D68411
42 lines
913 B
LLVM
42 lines
913 B
LLVM
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
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; Function Attrs: nounwind
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define void @dcbf_test(i8* %a) {
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entry:
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tail call void @llvm.ppc.dcbf(i8* %a)
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; CHECK-LABEL: @dcbf_test
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; CHECK: dcbf 0, r3
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; CHECK-NEXT: blr
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ret void
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}
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declare void @llvm.ppc.dcbf(i8*)
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; Function Attrs: nounwind
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define void @dcbfl_test(i8* %a) {
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entry:
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tail call void @llvm.ppc.dcbfl(i8* %a)
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; CHECK-LABEL: @dcbfl_test
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; CHECK: dcbfl 0, r3
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; CHECK-NEXT: blr
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ret void
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}
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declare void @llvm.ppc.dcbfl(i8*)
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; Function Attrs: nounwind
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define void @dcbflp_test(i8* %a) {
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entry:
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%add.a = getelementptr inbounds i8, i8* %a, i64 3
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tail call void @llvm.ppc.dcbflp(i8* %add.a)
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; CHECK-LABEL: @dcbflp_test
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; CHECK: addi r3, r3, 3
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; CHECK-NEXT: dcbflp 0, r3
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; CHECK-NEXT: blr
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ret void
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}
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declare void @llvm.ppc.dcbflp(i8*)
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