2d0f20cc04
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
28 lines
833 B
LLVM
28 lines
833 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
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define i64 @foo(i64 %t, i64 %u) nounwind {
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; X32-LABEL: foo:
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; X32: # %bb.0:
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %ecx, %eax
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; X32-NEXT: mull %esi
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; X32-NEXT: imull {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: addl %ecx, %edx
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; X32-NEXT: imull {{[0-9]+}}(%esp), %esi
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; X32-NEXT: addl %esi, %edx
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; X32-NEXT: popl %esi
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; X32-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: imulq %rsi, %rax
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; X64-NEXT: retq
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%k = mul i64 %t, %u
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ret i64 %k
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}
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