80aa2290fb
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
86 lines
2.4 KiB
YAML
86 lines
2.4 KiB
YAML
# RUN: llc -mtriple x86_64-- -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s
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# Check the TCRETURNdi64cc optimization.
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--- |
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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define i64 @test(i64 %arg, i8* %arg1) optsize {
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%tmp = icmp ult i64 %arg, 100
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br i1 %tmp, label %1, label %4
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%tmp3 = icmp ult i64 %arg, 10
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br i1 %tmp3, label %2, label %3
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%tmp5 = tail call i64 @f1(i8* %arg1, i64 %arg)
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ret i64 %tmp5
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%tmp7 = tail call i64 @f2(i8* %arg1, i64 %arg)
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ret i64 %tmp7
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ret i64 123
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}
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declare i64 @f1(i8*, i64)
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declare i64 @f2(i8*, i64)
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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- { reg: '$rsi' }
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body: |
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bb.0:
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successors: %bb.1, %bb.4
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liveins: $rdi, $rsi
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$rax = COPY $rdi
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CMP64ri8 $rax, 99, implicit-def $eflags
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JCC_1 %bb.4, 7, implicit $eflags
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JMP_1 %bb.1
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; CHECK: bb.1:
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; CHECK-NEXT: successors: %bb.2({{[^)]+}}){{$}}
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; CHECK-NEXT: liveins: $rax, $rsi
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; CHECK-NEXT: {{^ $}}
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; CHECK-NEXT: $rdi = COPY $rsi
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; CHECK-NEXT: $rsi = COPY $rax
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; CHECK-NEXT: CMP64ri8 $rax, 9, implicit-def $eflags
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; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 6, csr_64, implicit $rsp, implicit $eflags, implicit $ssp, implicit $rsp, implicit $rdi, implicit $rsi, implicit $rdi, implicit-def $rdi, implicit $hsi, implicit-def $hsi, implicit $sih, implicit-def $sih, implicit $sil, implicit-def $sil, implicit $si, implicit-def $si, implicit $esi, implicit-def $esi, implicit $rsi, implicit-def $rsi, implicit $hdi, implicit-def $hdi, implicit $dih, implicit-def $dih, implicit $dil, implicit-def $dil, implicit $di, implicit-def $di, implicit $edi, implicit-def $edi
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bb.1:
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successors: %bb.2, %bb.3
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liveins: $rax, $rsi
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CMP64ri8 $rax, 9, implicit-def $eflags
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JCC_1 %bb.3, 7, implicit $eflags
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JMP_1 %bb.2
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bb.2:
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liveins: $rax, $rsi
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$rdi = COPY $rsi
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$rsi = COPY $rax
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TCRETURNdi64 @f1, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
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; CHECK: bb.2:
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; CHECK-NEXT: liveins: $rdi, $rsi
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; CHECK-NEXT: {{^ $}}
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; CHECK-NEXT: TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
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bb.3:
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liveins: $rax, $rsi
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$rdi = COPY $rsi
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$rsi = COPY $rax
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TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
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bb.4:
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dead $eax = MOV32ri 123, implicit-def $rax
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RET 0, $rax
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...
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