shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
David Green e16cc8ed46
[AArch64] Guard for 128bit vectors in mull combine. (#169839) 
The test case generates a extract_subvector(index) leading into a mul.
Make sure we don't try and treat the scalable vector extract as a 128bit
vector in the mull combine.

Fixes #168912
2025-11-28 12:06:17 +00:00
..
AArch64
[AArch64] Guard for 128bit vectors in mull combine. (#169839)
2025-11-28 12:06:17 +00:00
AMDGPU
[AMDGPU] Remove odd syntax in some RUN lines. NFC. (#169831)
2025-11-27 17:00:54 +00:00
ARC
…
ARM
[DAG] Add strictfp implicit def reg after metadata. (#168282)
2025-11-17 10:57:21 +00:00
AVR
[AVR] Fix occasional corruption in stack passed params
2025-10-24 08:45:10 +08:00
BPF
[BPF] Allow libcalls behind a feature gate (#168442)
2025-11-24 09:02:50 -08:00
CSKY
…
DirectX
[NFC] [DirectX] Make DirectX codegen test CBufferAccess/gep-ce-two-uses.ll more strict (#169855)
2025-11-27 13:58:47 -08:00
Generic
[IR] llvm.reloc.none intrinsic for no-op symbol references (#147427)
2025-11-06 08:52:46 -08:00
Hexagon
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
Inputs
…
Lanai
…
LoongArch
[LoongArch] Make rotl/rotr custom for lsx/lasx (#161154)
2025-11-28 15:28:19 +08:00
M68k
…
Mips
[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)
2025-11-25 00:02:37 -05:00
MIR
Add IR and codegen support for deactivation symbols.
2025-11-26 12:37:09 -08:00
MIR2Vec
[AMX][NFC] Organize tilerow (#168193)
2025-11-28 15:02:47 +08:00
MLRegAlloc
[MLGO] Remove Extra Dev Mode Features (#167273)
2025-11-10 08:40:28 -08:00
MSP430
MSP430: Remove more default compiler-rt calls (#164752)
2025-10-23 15:23:02 +09:00
NVPTX
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
PowerPC
[PowerPC ]convert (setcc (and X, 1), 0, eq) to XORI (and X, 1), 1 (#168384)
2025-11-25 13:16:39 -05:00
RISCV
[RISCV] Remove intrinsic declarations in tests, NFC (#167474)
2025-11-26 17:25:07 +08:00
SPARC
[Sparc] Optimize compare instruction (#167140)
2025-11-14 23:11:38 +07:00
SPIRV
[SPIRV][AMD] Disable SPV_KHR_float_control2 for AMD flavored SPIRV (#169659)
2025-11-27 16:16:21 +01:00
SystemZ
[SystemZ] Serialize ada entry flags (#169395)
2025-11-27 08:14:43 -05:00
Thumb
[test][ARM] Remove unsafe-fp-math-uses (NFC) (#164744)
2025-10-23 15:07:46 +08:00
Thumb2
[ARM] Remove IR from mve vpt mir tests. NFC
2025-11-27 09:16:30 +00:00
VE
…
WebAssembly
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
WinCFGuard
…
WinEH
…
X86
[X86] rem-vector-lkk.ll - improve CPU coverage to cover all x86-64 levels (#169805)
2025-11-27 14:31:32 +00:00
XCore
…
Xtensa
[Xtensa] Fix S32C1I instruction encoding and copyPhysReg. (#165174)
2025-11-05 20:27:11 +03:00