573ca36753
The `masked.load`, `masked.store`, `masked.gather` and `masked.scatter` intrinsics currently accept a separate alignment immarg. Replace this with an `align` attribute on the pointer / vector of pointers argument. This is the standard representation for alignment information on intrinsics, and is already used by all other memory intrinsics. This means the signatures now match llvm.expandload, llvm.vp.load, etc. (Things like llvm.memcpy used to have a separate alignment argument as well, but were already migrated a long time ago.) It's worth noting that the masked.gather and masked.scatter intrinsics previously accepted a zero alignment to indicate the ABI type alignment of the element type. This special case is gone now: If the align attribute is omitted, the implied alignment is 1, as usual. If ABI alignment is desired, it needs to be explicitly emitted (which the IRBuilder API already requires anyway).
105 lines
4.9 KiB
LLVM
105 lines
4.9 KiB
LLVM
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=CHECK-VF4UF1
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; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=CHECK-VF4UF2
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; We vectorize this first order recurrence, with a set of insertelements for
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; each unrolled part. Make sure these insertelements are generated in-order,
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; because the shuffle of the first order recurrence will be added after the
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; insertelement of the last part UF - 1, assuming the latter appears after the
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; insertelements of all other parts.
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;
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; int PR33613(double *b, double j, int d) {
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; int a = 0;
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; for(int i = 0; i < 10240; i++, b+=25) {
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; double f = b[d]; // Scalarize to form insertelements
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; if (j * f)
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; a++;
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; j = f;
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; }
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; return a;
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; }
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;
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define i32 @PR33613(ptr %b, double %j, i32 %d) #0 {
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; CHECK-VF4UF2-LABEL: @PR33613
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; CHECK-VF4UF2: vector.body
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; CHECK-VF4UF2: %[[VEC_RECUR:.*]] = phi <vscale x 4 x double> [ {{.*}}, %vector.ph ], [ {{.*}}, %vector.body ]
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; CHECK-VF4UF2: %[[SPLICE1:.*]] = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %[[VEC_RECUR]], <vscale x 4 x double> {{.*}}, i32 -1)
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; CHECK-VF4UF2-NEXT: %[[SPLICE2:.*]] = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %{{.*}}, <vscale x 4 x double> %{{.*}}, i32 -1)
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; CHECK-VF4UF2-NOT: insertelement <vscale x 4 x double>
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; CHECK-VF4UF2: middle.block
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entry:
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%idxprom = sext i32 %d to i64
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br label %for.body
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for.cond.cleanup:
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%a.1.lcssa = phi i32 [ %a.1, %for.body ]
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ret i32 %a.1.lcssa
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for.body:
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%b.addr.012 = phi ptr [ %b, %entry ], [ %add.ptr, %for.body ]
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%i.011 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
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%a.010 = phi i32 [ 0, %entry ], [ %a.1, %for.body ]
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%j.addr.09 = phi double [ %j, %entry ], [ %0, %for.body ]
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%arrayidx = getelementptr inbounds double, ptr %b.addr.012, i64 %idxprom
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%0 = load double, ptr %arrayidx, align 8
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%mul = fmul double %j.addr.09, %0
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%tobool = fcmp une double %mul, 0.000000e+00
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%inc = zext i1 %tobool to i32
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%a.1 = add nsw i32 %a.010, %inc
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%inc1 = add nuw nsw i32 %i.011, 1
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%add.ptr = getelementptr inbounds double, ptr %b.addr.012, i64 25
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%exitcond = icmp eq i32 %inc1, 10240
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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}
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; PR34711: given three consecutive instructions such that the first will be
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; widened, the second is a cast that will be widened and needs to sink after the
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; third, and the third is a first-order-recurring load that will be replicated
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; instead of widened. Although the cast and the first instruction will both be
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; widened, and are originally adjacent to each other, make sure the replicated
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; load ends up appearing between them.
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;
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; void PR34711(short[2] *a, int *b, int *c, int n) {
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; for(int i = 0; i < n; i++) {
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; c[i] = 7;
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; b[i] = (a[i][0] * a[i][1]);
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; }
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; }
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;
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; Check that the sext sank after the load in the vector loop.
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define void @PR34711(ptr %a, ptr %b, ptr %c, i64 %n) #0 {
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; CHECK-VF4UF1-LABEL: @PR34711
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; CHECK-VF4UF1: vector.body
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; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi <vscale x 4 x i16> [ %vector.recur.init, %vector.ph ], [ %[[MGATHER:.*]], %vector.body ]
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; CHECK-VF4UF1: %[[MGATHER]] = call <vscale x 4 x i16> @llvm.masked.gather.nxv4i16.nxv4p0(<vscale x 4 x ptr> {{.*}}, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i16> poison)
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; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %[[VEC_RECUR]], <vscale x 4 x i16> %[[MGATHER]], i32 -1)
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; CHECK-VF4UF1-NEXT: %[[SXT1:.*]] = sext <vscale x 4 x i16> %[[SPLICE]] to <vscale x 4 x i32>
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; CHECK-VF4UF1-NEXT: %[[SXT2:.*]] = sext <vscale x 4 x i16> %[[MGATHER]] to <vscale x 4 x i32>
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; CHECK-VF4UF1-NEXT: mul nsw <vscale x 4 x i32> %[[SXT2]], %[[SXT1]]
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entry:
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%.pre = load i16, ptr %a
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br label %for.body
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for.body:
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%0 = phi i16 [ %.pre, %entry ], [ %1, %for.body ]
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arraycidx = getelementptr inbounds i32, ptr %c, i64 %indvars.iv
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%cur.index = getelementptr inbounds [2 x i16], ptr %a, i64 %indvars.iv, i64 1
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store i32 7, ptr %arraycidx ; 1st instruction, to be widened.
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%conv = sext i16 %0 to i32 ; 2nd, cast to sink after third.
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%1 = load i16, ptr %cur.index ; 3rd, first-order-recurring load not widened.
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%conv3 = sext i16 %1 to i32
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%mul = mul nsw i32 %conv3, %conv
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%arrayidx5 = getelementptr inbounds i32, ptr %b, i64 %indvars.iv
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store i32 %mul, ptr %arrayidx5
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0
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for.end:
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ret void
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}
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attributes #0 = { vscale_range(1, 16) }
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!0 = distinct !{!0, !1}
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!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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