511c9c0648
Some analysis/transformation, e.g., predicate info/ mem ssa, insert instruction annotations as comments, referring to https://github.com/llvm/llvm-project/pull/165249#discussion_r2466200672. This PR makes UTC support checking these instruction annotations with an extra UTC option `-check-inst-comments`. E.g., Before: ```LLVM ; CHECK: [[Z_0:%.*]] = bitcast i1 [[Z]] to i1 ``` After: ```LLVM ; CHECK-NEXT: ; branch predicate info { TrueEdge: 0 Comparison: [[Z]] = and i1 [[XZ]], [[YZ]] Edge: [label [[TMP0:%.*]],label %nope], RenamedOp: [[Z]] } ; CHECK-NEXT: [[Z_0:%.*]] = bitcast i1 [[Z]] to i1 ``` This PR also regenerates all UTC-generated tests for PredicateInfo; No MemSSA test is updated, as there are no UTC-generated tests designated for `print<memoryssa>`.
73 lines
2.9 KiB
LLVM
73 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-inst-comments
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; RUN: opt -passes=print-predicateinfo -disable-output < %s 2>&1 | FileCheck %s
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define i1 @f(i32 %x, i1 %y) {
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; CHECK-LABEL: @f(
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; CHECK-NEXT: br i1 [[Y:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
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; CHECK: bb0:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
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; CHECK-NEXT: ; branch predicate info { TrueEdge: 1 Comparison: [[CMP]] = icmp sge i32 [[X]], 0 Edge: [label [[BB0]],label [[BB2:%.*]]], RenamedOp: [[X]] }
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; CHECK-NEXT: [[X_0:%.*]] = bitcast i32 [[X]] to i32
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; CHECK-NEXT: br i1 [[CMP]], label [[BB2]], label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[X2:%.*]] = add nuw nsw i32 [[X]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X2]], 2
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; CHECK-NEXT: ; branch predicate info { TrueEdge: 1 Comparison: [[CMP2]] = icmp sge i32 [[X2]], 2 Edge: [label [[BB1]],label [[BB2]]], RenamedOp: [[X2]] }
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; CHECK-NEXT: [[X2_0:%.*]] = bitcast i32 [[X2]] to i32
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; CHECK-NEXT: br i1 [[CMP2]], label [[BB2]], label [[BB3]]
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; CHECK: bb2:
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; CHECK-NEXT: [[X3:%.*]] = phi i32 [ [[X_0]], [[BB0]] ], [ [[X2_0]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i1 false
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;
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br i1 %y, label %bb0, label %bb1
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bb0:
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%cmp = icmp sge i32 %x, 0 ; x > 0
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br i1 %cmp, label %bb2, label %bb3
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bb1:
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%x2 = add nsw nuw i32 %x, 1
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%cmp2 = icmp sge i32 %x2, 2 ; x+1 > 2 / x > 1
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br i1 %cmp2, label %bb2, label %bb3
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bb2:
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%x3 = phi i32 [ %x, %bb0 ], [ %x2, %bb1 ]
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br label %bb3
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bb3:
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ret i1 0
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}
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define i1 @g(i32 %x, i1 %y) {
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; CHECK-LABEL: @g(
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; CHECK-NEXT: br i1 [[Y:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
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; CHECK: bb0:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
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; CHECK-NEXT: ; branch predicate info { TrueEdge: 0 Comparison: [[CMP]] = icmp sge i32 [[X]], 0 Edge: [label [[BB0]],label [[BB2:%.*]]], RenamedOp: [[X]] }
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; CHECK-NEXT: [[X_0:%.*]] = bitcast i32 [[X]] to i32
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; CHECK-NEXT: br i1 [[CMP]], label [[BB3:%.*]], label [[BB2]]
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; CHECK: bb1:
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; CHECK-NEXT: [[X2:%.*]] = add nuw nsw i32 [[X]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i32 [[X2]], 2
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; CHECK-NEXT: ; branch predicate info { TrueEdge: 0 Comparison: [[CMP2]] = icmp sge i32 [[X2]], 2 Edge: [label [[BB1]],label [[BB2]]], RenamedOp: [[X2]] }
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; CHECK-NEXT: [[X2_0:%.*]] = bitcast i32 [[X2]] to i32
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; CHECK-NEXT: br i1 [[CMP2]], label [[BB3]], label [[BB2]]
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; CHECK: bb2:
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; CHECK-NEXT: [[X3:%.*]] = phi i32 [ [[X_0]], [[BB0]] ], [ [[X2_0]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i1 false
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;
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br i1 %y, label %bb0, label %bb1
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bb0:
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%cmp = icmp sge i32 %x, 0 ; x > 0
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br i1 %cmp, label %bb3, label %bb2
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bb1:
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%x2 = add nsw nuw i32 %x, 1
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%cmp2 = icmp sge i32 %x2, 2 ; x+1 > 2 / x > 1
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br i1 %cmp2, label %bb3, label %bb2
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bb2:
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%x3 = phi i32 [ %x, %bb0 ], [ %x2, %bb1 ]
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br label %bb3
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bb3:
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ret i1 0
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}
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