e246d1615e
We need to be able to address emergency spill slots without requiring a register scavenging. This requires the emergency spill slot to be near the SP or the FP to keep the offset small enough. If there is a large reserved call frame, we can't keep the emergency spill slot near SP. But we might not have a frame pointer. This patch forces the use of a frame pointer when the max reserved call frame is large so we can keep the emergency spill slot near it. This idea is borrowed from AArch64. Multiple MIR tests had to be updated to set the max call frame size as the reserved registers are frozen before mirFileLoaded is called. I copied mirFileLoaded from AArch64, but it appears the register freezing moved after the AArch64 code was written. Fixes #180199.
299 lines
11 KiB
C++
299 lines
11 KiB
C++
//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "GISel/RISCVCallLowering.h"
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#include "GISel/RISCVLegalizerInfo.h"
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#include "RISCV.h"
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#include "RISCVFrameLowering.h"
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#include "RISCVSelectionDAGInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "RISCVGenSubtargetInfo.inc"
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#define GET_RISCV_MACRO_FUSION_PRED_IMPL
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#include "RISCVGenMacroFusion.inc"
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namespace llvm::RISCVTuneInfoTable {
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#define GET_RISCVTuneInfoTable_IMPL
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#include "RISCVGenSearchableTables.inc"
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} // namespace llvm::RISCVTuneInfoTable
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static cl::opt<unsigned> RVVVectorLMULMax(
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"riscv-v-fixed-length-vector-lmul-max",
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cl::desc("The maximum LMUL value to use for fixed length vectors. "
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"Fractional LMUL values are not supported."),
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cl::init(8), cl::Hidden);
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static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
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"riscv-disable-using-constant-pool-for-large-ints",
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cl::desc("Disable using constant pool for large integers."),
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cl::init(false), cl::Hidden);
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static cl::opt<unsigned> RISCVMaxBuildIntsCost(
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"riscv-max-build-ints-cost",
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cl::desc("The maximum cost used for building integers."), cl::init(0),
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cl::Hidden);
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static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
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cl::desc("Enable the use of AA during codegen."));
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static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
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"riscv-min-jump-table-entries", cl::Hidden,
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cl::desc("Set minimum number of entries to use a jump table on RISCV"));
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static cl::opt<bool> UseMIPSLoadStorePairsOpt(
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"use-riscv-mips-load-store-pairs",
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cl::desc("Enable the load/store pair optimization pass"), cl::init(false),
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cl::Hidden);
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static cl::opt<bool> UseMIPSCCMovInsn("use-riscv-mips-ccmov",
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cl::desc("Use 'mips.ccmov' instruction"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool> EnablePExtSIMDCodeGen(
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"riscv-enable-p-ext-simd-codegen",
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cl::desc("Turn on P Extension SIMD codegen(This is a temporary switch "
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"where only partial codegen is currently supported)"),
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cl::init(false), cl::Hidden);
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void RISCVSubtarget::anchor() {}
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RISCVSubtarget &
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RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
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StringRef TuneCPU, StringRef FS,
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StringRef ABIName) {
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// Determine default and user-specified characteristics
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bool Is64Bit = TT.isArch64Bit();
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if (CPU.empty() || CPU == "generic")
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CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
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if (TuneCPU.empty())
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TuneCPU = CPU;
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if (TuneCPU == "generic")
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TuneCPU = Is64Bit ? "generic-rv64" : "generic-rv32";
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TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(TuneCPU);
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// If there is no TuneInfo for this CPU, we fail back to generic.
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if (!TuneInfo)
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TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo("generic");
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assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
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ParseSubtargetFeatures(CPU, TuneCPU, FS);
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RISCV::updateCZceFeatureImplications(*this);
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// Re-sync the flags.
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HasStdExtZcd = hasFeature(RISCV::FeatureStdExtZcd);
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HasStdExtZcf = hasFeature(RISCV::FeatureStdExtZcf);
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HasStdExtC = hasFeature(RISCV::FeatureStdExtC);
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HasStdExtZce = hasFeature(RISCV::FeatureStdExtZce);
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TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
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RISCVFeatures::validate(TT, getFeatureBits());
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return *this;
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}
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
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StringRef TuneCPU, StringRef FS,
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StringRef ABIName, unsigned RVVVectorBitsMin,
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unsigned RVVVectorBitsMax,
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const TargetMachine &TM)
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: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
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IsLittleEndian(TT.isLittleEndian()), RVVVectorBitsMin(RVVVectorBitsMin),
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RVVVectorBitsMax(RVVVectorBitsMax),
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FrameLowering(
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initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
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InstrInfo(*this), TLInfo(TM, *this) {
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TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
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}
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RISCVSubtarget::~RISCVSubtarget() = default;
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const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
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return TSInfo.get();
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}
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const CallLowering *RISCVSubtarget::getCallLowering() const {
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if (!CallLoweringInfo)
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CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
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return CallLoweringInfo.get();
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}
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InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
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if (!InstSelector) {
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InstSelector.reset(createRISCVInstructionSelector(
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*static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
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*this, *getRegBankInfo()));
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}
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return InstSelector.get();
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}
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const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
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if (!Legalizer)
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Legalizer.reset(new RISCVLegalizerInfo(*this));
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return Legalizer.get();
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}
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const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
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if (!RegBankInfo)
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RegBankInfo.reset(new RISCVRegisterBankInfo(getHwMode()));
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return RegBankInfo.get();
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}
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bool RISCVSubtarget::useConstantPoolForLargeInts() const {
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return !RISCVDisableUsingConstantPoolForLargeInts;
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}
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bool RISCVSubtarget::enablePExtSIMDCodeGen() const {
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return HasStdExtP && EnablePExtSIMDCodeGen;
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}
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// Returns true if VT is a P extension packed SIMD type that fits in XLen.
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bool RISCVSubtarget::isPExtPackedType(MVT VT) const {
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if (!enablePExtSIMDCodeGen())
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return false;
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if (is64Bit())
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return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
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return VT == MVT::v4i8 || VT == MVT::v2i16;
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}
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unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
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// Loading integer from constant pool needs two instructions (the reason why
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// the minimum cost is 2): an address calculation instruction and a load
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// instruction. Usually, address calculation and instructions used for
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// building integers (addi, slli, etc.) can be done in one cycle, so here we
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// set the default cost to (LoadLatency + 1) if no threshold is provided.
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return RISCVMaxBuildIntsCost == 0
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? getSchedModel().LoadLatency + 1
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: std::max<unsigned>(2, RISCVMaxBuildIntsCost);
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}
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unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
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assert(hasVInstructions() &&
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"Tried to get vector length without Zve or V extension support!");
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// ZvlLen specifies the minimum required vlen. The upper bound provided by
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// riscv-v-vector-bits-max should be no less than it.
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if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
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report_fatal_error("riscv-v-vector-bits-max specified is lower "
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"than the Zvl*b limitation");
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return RVVVectorBitsMax;
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}
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unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
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assert(hasVInstructions() &&
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"Tried to get vector length without Zve or V extension support!");
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if (RVVVectorBitsMin == -1U)
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return ZvlLen;
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// ZvlLen specifies the minimum required vlen. The lower bound provided by
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// riscv-v-vector-bits-min should be no less than it.
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if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
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report_fatal_error("riscv-v-vector-bits-min specified is lower "
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"than the Zvl*b limitation");
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return RVVVectorBitsMin;
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}
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unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
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assert(hasVInstructions() &&
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"Tried to get vector length without Zve or V extension support!");
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assert(RVVVectorLMULMax <= 8 &&
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llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
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"V extension requires a LMUL to be at most 8 and a power of 2!");
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return llvm::bit_floor(std::clamp<unsigned>(RVVVectorLMULMax, 1, 8));
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}
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bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
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return hasVInstructions() &&
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getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
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}
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bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
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bool RISCVSubtarget::enableMachinePipeliner() const {
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return getSchedModel().hasInstrSchedModel();
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}
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void RISCVSubtarget::mirFileLoaded(MachineFunction &MF) const {
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// We usually compute max call frame size after ISel. Do the computation now
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// if the .mir file didn't specify it. Note that this will probably give you
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// bogus values after PEI has eliminated the callframe setup/destroy pseudo
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// instructions, specify explicitly if you need it to be correct.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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if (!MFI.isMaxCallFrameSizeComputed())
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MFI.computeMaxCallFrameSize(MF);
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}
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/// Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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bool RISCVSubtarget::useAA() const { return UseAA; }
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unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
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return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
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? RISCVMinimumJumpTableEntries
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: TuneInfo->MinimumJumpTableEntries;
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}
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void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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const SchedRegion &Region) const {
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// Do bidirectional scheduling since it provides a more balanced scheduling
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// leading to better performance. This will increase compile time.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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// Disabling the latency heuristic can reduce the number of spills/reloads but
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// will cause some regressions on some cores.
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Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
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// Spilling is generally expensive on all RISC-V cores, so always enable
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// register-pressure tracking. This will increase compile time.
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Policy.ShouldTrackPressure = true;
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}
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void RISCVSubtarget::overridePostRASchedPolicy(
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MachineSchedPolicy &Policy, const SchedRegion &Region) const {
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MISched::Direction PostRASchedDirection = getPostRASchedDirection();
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if (PostRASchedDirection == MISched::TopDown) {
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Policy.OnlyTopDown = true;
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Policy.OnlyBottomUp = false;
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} else if (PostRASchedDirection == MISched::BottomUp) {
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = true;
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} else if (PostRASchedDirection == MISched::Bidirectional) {
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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}
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bool RISCVSubtarget::useMIPSLoadStorePairs() const {
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return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
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}
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bool RISCVSubtarget::useMIPSCCMovInsn() const {
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return UseMIPSCCMovInsn && HasVendorXMIPSCMov;
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}
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