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llvm-project/llvm/test/CodeGen
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Ben Shi e32cf690df [RISCV] Optimize (add (mul r, c0), c1) 
Optimize (add (mul x, c0), c1) ->
         (add (mul (add x, c1/c0+1), c0), c1%c0-c0),
if c1/c0+1 and c1%c0-c0 are simm12, while c1 is not.

Optimize (add (mul x, c0), c1) ->
         (add (mul (add x, c1/c0-1), c0), c1%c0+c0),
if c1/c0-1 and c1%c0+c0 are simm12, while c1 is not.

Reviewed By: craig.topper, asb

Differential Revision: https://reviews.llvm.org/D111141
2021-11-08 02:58:25 +00:00
..
AArch64
[AArch64] Rewrite and update fcvt-fixed.ll. NFC
2021-11-07 18:11:49 +00:00
AMDGPU
[AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values.
2021-11-04 21:50:18 +01:00
ARC
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
2021-09-10 13:04:08 -07:00
ARM
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
AVR
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
BPF
BPF: Support btf_type_tag attribute
2021-11-04 17:01:36 -07:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
Hexagon
[Hexagon] Add machine verification to some tests
2021-11-02 15:41:30 +00:00
Inputs
…
Lanai
[Lanai] implement wide immediate support
2021-09-10 10:54:43 +00:00
M68k
[M68k][test] Migrate the remaining fixup and relaxation tests
2021-09-04 16:27:13 -07:00
Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
[NVPTX] Mark special registers as reserved
2021-11-03 15:48:04 +03:00
PowerPC
[AsmPrinter][ORE] use correct opcode name
2021-11-08 01:51:24 +00:00
RISCV
[RISCV] Optimize (add (mul r, c0), c1)
2021-11-08 02:58:25 +00:00
SPARC
[SparcISelLowering] avoid emitting libcalls to __muloti4 and __mulodi4
2021-10-29 13:14:09 -07:00
SystemZ
[SystemZ] Improvement of emitMemMemWrapper()
2021-10-26 17:03:01 +02:00
Thumb
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
Thumb2
[DAGCombiner] add fold for vselect based on mask of signbit, part 2
2021-11-05 15:02:12 -04:00
VE
[VE][NFC] correct bitmasking in popcnt expansion test
2021-10-25 13:55:58 +02:00
WebAssembly
[WebAssembly] Add prototype relaxed float to int trunc instructions
2021-10-28 14:01:53 -07:00
WinCFGuard
…
WinEH
…
X86
[X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source
2021-11-07 21:24:55 +00:00
XCore
…