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llvm-project/llvm/test/CodeGen
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Matt Arsenault e46badd4e9 GlobalISel: Have lowerLoad scalarize unaligned vectors 
This could be smarter by picking an ideal type, or at least splitting
the vector in half first. Also handles lower for non-power-of-2,
non-extending vector loads.

Currently this just avoids failing to legalize some odd vector AMDGPU
tests, but is a step towards removing the split logic from the
NarrowScalar logic.
2021-07-30 13:23:29 -04:00
..
AArch64
GlobalISel/AArch64: don't optimize away redundant branches at -O0
2021-07-29 16:04:22 -07:00
AMDGPU
GlobalISel: Have lowerLoad scalarize unaligned vectors
2021-07-30 13:23:29 -04:00
ARC
…
ARM
[MBP] findBestLoopTopHelper should exit if OldTop is not a chain header
2021-07-28 19:00:45 -07:00
AVR
[AVR] Only support sp, r0 and r1 in llvm.read_register
2021-07-24 14:03:27 +02:00
BPF
[BPF] Use elementtype attribute for preserve.array/struct.index intrinsics
2021-07-17 11:09:18 +02:00
Generic
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX
2021-07-26 23:21:38 +00:00
Hexagon
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
2021-07-27 18:36:28 -05:00
Inputs
…
Lanai
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
M68k
[M68k][GloballSel] LegalizerInfo implementation
2021-07-15 13:00:43 -06:00
Mips
GlobalISel/AArch64: don't optimize away redundant branches at -O0
2021-07-29 16:04:22 -07:00
MIR
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
MSP430
…
NVPTX
[NVPTX] Add select(cc,binop(),binop()) fast-math tests
2021-07-18 15:30:24 +01:00
PowerPC
[PowerPC] Fix issue where hint was providing the incorrect regsiter class.
2021-07-29 21:10:45 -05:00
RISCV
Optimize mul in the zba extension with SH*ADD
2021-07-30 08:36:28 +08:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
[SystemZ][z/OS] Initial code to generate assembly files on z/OS
2021-07-27 11:29:15 -04:00
Thumb
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
Thumb2
[ARM] Attempt to distribute reductions
2021-07-30 14:48:31 +01:00
VE
[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.
2021-06-29 11:00:11 -07:00
WebAssembly
[WebAssembly] Codegen for extmul SIMD instructions
2021-07-27 08:41:30 -07:00
WinCFGuard
…
WinEH
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X86
[X86] Add some initial tests for frozen constant folds
2021-07-30 16:37:02 +01:00
XCore
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00