6175fcf01f
Update CodeGen regression tests with marker at first line telling it's auto-generated by the script, under PowerPC directory. For some reason, these tests are generated but manually written, which makes things unclear when someone's change affecting them. However, some tests only show simple change after re-generated, like extra blank lines, disappearing '.localentry', etc. Besides, some tests are generated but added checks for debug output. This commit doesn't try updating them.
131 lines
4.4 KiB
LLVM
131 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE
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define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
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; BE-LABEL: test1:
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; BE: # %bb.0:
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; BE-NEXT: lxvw4x 0, 0, 3
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; BE-NEXT: vspltisb 2, -1
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; BE-NEXT: vslw 2, 2, 2
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; BE-NEXT: xxland 0, 0, 34
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; BE-NEXT: stxvw4x 0, 0, 3
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; BE-NEXT: lxvw4x 0, 0, 4
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; BE-NEXT: xxlandc 0, 0, 34
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; BE-NEXT: stxvw4x 0, 0, 4
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; BE-NEXT: lxvw4x 0, 0, 5
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; BE-NEXT: xvabssp 0, 0
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; BE-NEXT: stxvw4x 0, 0, 5
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; BE-NEXT: blr
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;
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; LE-LABEL: test1:
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; LE: # %bb.0:
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; LE-NEXT: lvx 2, 0, 3
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; LE-NEXT: vspltisb 3, -1
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; LE-NEXT: vslw 3, 3, 3
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; LE-NEXT: xxland 34, 34, 35
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; LE-NEXT: stvx 2, 0, 3
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; LE-NEXT: lvx 2, 0, 4
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; LE-NEXT: xxlandc 34, 34, 35
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; LE-NEXT: stvx 2, 0, 4
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; LE-NEXT: lvx 2, 0, 5
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; LE-NEXT: xvabssp 34, 34
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; LE-NEXT: stvx 2, 0, 5
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; LE-NEXT: blr
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%tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
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%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp4, <4 x i32>* %P1
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%tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
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%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp9, <4 x i32>* %P2
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%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp13, <4 x float>* %P3
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ret void
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}
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define <4 x i32> @test_30() nounwind {
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; CHECK-LABEL: test_30:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 2, 15
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; CHECK-NEXT: vadduwm 2, 2, 2
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; CHECK-NEXT: blr
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ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
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}
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define <4 x i32> @test_29() nounwind {
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; CHECK-LABEL: test_29:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 2, 13
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; CHECK-NEXT: vsubuwm 2, 2, 3
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; CHECK-NEXT: blr
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ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
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}
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define <8 x i16> @test_n30() nounwind {
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; CHECK-LABEL: test_n30:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltish 2, -15
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; CHECK-NEXT: vadduhm 2, 2, 2
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; CHECK-NEXT: blr
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ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
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}
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define <16 x i8> @test_n104() nounwind {
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; CHECK-LABEL: test_n104:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisb 2, -13
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; CHECK-NEXT: vslb 2, 2, 2
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; CHECK-NEXT: blr
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ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
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}
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define <4 x i32> @test_vsldoi() nounwind {
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; CHECK-LABEL: test_vsldoi:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 2, 2
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; CHECK-NEXT: vsldoi 2, 2, 2, 1
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; CHECK-NEXT: blr
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ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
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}
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define <8 x i16> @test_vsldoi_65023() nounwind {
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; CHECK-LABEL: test_vsldoi_65023:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltish 2, -3
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; CHECK-NEXT: vsldoi 2, 2, 2, 1
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; CHECK-NEXT: blr
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ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
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}
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define <4 x i32> @test_vsldoi_x16() nounwind {
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; CHECK-LABEL: test_vsldoi_x16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 2, -3
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; CHECK-NEXT: vsldoi 2, 2, 2, 2
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; CHECK-NEXT: blr
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ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073>
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}
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define <4 x i32> @test_vsldoi_x24() nounwind {
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; CHECK-LABEL: test_vsldoi_x24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 2, -3
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; CHECK-NEXT: vsldoi 2, 2, 2, 3
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; CHECK-NEXT: blr
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ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433>
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}
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define <4 x i32> @test_rol() nounwind {
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; CHECK-LABEL: test_rol:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 2, -12
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; CHECK-NEXT: vrlw 2, 2, 2
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; CHECK-NEXT: blr
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ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
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}
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