524d8fa9a5
This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
73 lines
2.5 KiB
LLVM
73 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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declare void @callee(i8*, i32*)
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define void @caller(i32 %n) {
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; RV32I-LABEL: caller:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -64
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; RV32I-NEXT: .cfi_def_cfa_offset 64
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; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
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; RV32I-NEXT: .cfi_offset ra, -4
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; RV32I-NEXT: .cfi_offset s0, -8
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; RV32I-NEXT: .cfi_offset s1, -12
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; RV32I-NEXT: addi s0, sp, 64
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; RV32I-NEXT: .cfi_def_cfa s0, 0
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; RV32I-NEXT: andi sp, sp, -64
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; RV32I-NEXT: mv s1, sp
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; RV32I-NEXT: addi a0, a0, 15
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; RV32I-NEXT: andi a0, a0, -16
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; RV32I-NEXT: sub a0, sp, a0
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; RV32I-NEXT: mv sp, a0
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; RV32I-NEXT: mv a1, s1
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; RV32I-NEXT: call callee@plt
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; RV32I-NEXT: addi sp, s0, -64
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; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 64
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: caller:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -64
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; RV64I-NEXT: .cfi_def_cfa_offset 64
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; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
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; RV64I-NEXT: .cfi_offset ra, -8
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; RV64I-NEXT: .cfi_offset s0, -16
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; RV64I-NEXT: .cfi_offset s1, -24
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; RV64I-NEXT: addi s0, sp, 64
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; RV64I-NEXT: .cfi_def_cfa s0, 0
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; RV64I-NEXT: andi sp, sp, -64
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; RV64I-NEXT: mv s1, sp
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: addi a0, a0, 15
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; RV64I-NEXT: addi a1, zero, 1
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; RV64I-NEXT: slli a1, a1, 33
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; RV64I-NEXT: addi a1, a1, -16
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: sub a0, sp, a0
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; RV64I-NEXT: mv sp, a0
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; RV64I-NEXT: mv a1, s1
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; RV64I-NEXT: call callee@plt
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; RV64I-NEXT: addi sp, s0, -64
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; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 64
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; RV64I-NEXT: ret
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%1 = alloca i8, i32 %n
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%2 = alloca i32, align 64
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call void @callee(i8* %1, i32 *%2)
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ret void
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}
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