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llvm-project/llvm/lib/Target/RISCV
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Brandon Wu 0e03199e81
[RISCV][llvm] Remove custom legalization of fixed-length vector SPLAT_VECTOR (#172870) 
BUILD_VECTOR is combined to SPLAT_VECTOR if operation action of
SPLAT_VECTOR is not Expand. However we already have custom handle of
BUILD_VECTOR for fixed-length vector which has explicit constant VL
instead of making it VLMAX if lowered through SPLAT_VECTOR.
2025-12-19 11:45:10 +08:00
..
AsmParser
[RISCV] Intrinsic Support for XCVelw (#129168)
2025-11-29 19:07:19 +11:00
Disassembler
[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349)
2025-10-21 18:27:21 -07:00
GISel
[RISCV][GISel] Legalize the G_FCANONICALIZE instruction (#166162)
2025-12-10 15:45:01 +08:00
MCA
[RISCVInsertVSETVLI] Don't allow getSEW/getLMUL to be called for hasSEWLMULRatioOnly(). NFC (#171554)
2025-12-09 22:06:15 -08:00
MCTargetDesc
[RISCV] Prefer li over pli in RISCVMatInt. (#172778)
2025-12-17 19:35:38 -08:00
TargetInfo
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
CMakeLists.txt
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCV.h
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCV.td
CodeGen: Make all targets override pseudos with pointers (#159881)
2025-11-26 14:57:14 +00:00
RISCVAsmPrinter.cpp
[RISCV] Add an OperandType to VMaskOp. NFC (#171926)
2025-12-11 20:03:47 -08:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543)
2025-12-08 06:09:03 +00:00
RISCVCombine.td
[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008)
2025-10-23 15:50:04 +08:00
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVDeadRegisterDefinitions.cpp
CodeGen: Remove TRI argument from getRegClass (#158225)
2025-11-10 15:43:55 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] 'Zalrsc' may permit non-base instructions (#165042)
2025-10-28 12:51:11 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add short forward branch support for qc.e.lb(u), qc.e.lh(u) and qc.e.lw (#172629)
2025-12-18 09:38:31 +05:30
RISCVFeatures.td
[RISCV] Add Xqci feature flag (#172608)
2025-12-18 21:32:49 +05:30
RISCVFoldMemOffset.cpp
…
RISCVFrameLowering.cpp
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
RISCVFrameLowering.h
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
RISCVGatherScatterLowering.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVGISel.td
[RISCV][NFC] Simplify Imm range checks (#170497)
2025-12-04 06:04:49 +01:00
RISCVIndirectBranchTracking.cpp
[RISCV] Emit lpad for function with returns-twice attribute (#170520)
2025-12-04 13:25:57 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Add OperandType for XSfmm TWiden. (#171572)
2025-12-10 13:05:55 -08:00
RISCVInsertWriteVXRM.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
RISCVInstrFormats.td
[RISCV] Use a tablegen class for AltFmtType. NFC (#163251)
2025-10-13 23:19:23 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
…
RISCVInstrInfo.cpp
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVInstrInfo.h
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVInstrInfo.td
[RISCV] Remove now unused ixlenimm Operand. NFC (#171896)
2025-12-11 14:46:47 -08:00
RISCVInstrInfoA.td
[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736)
2025-12-10 20:43:46 -08:00
RISCVInstrInfoC.td
[TableGen][DecoderEmitter][RISCV] Always handle bits<0> (#159951)
2025-09-22 20:50:17 +03:00
RISCVInstrInfoD.td
[RISCV] Enable rematerialization for scalar loads (#166774)
2025-11-24 18:14:19 +08:00
RISCVInstrInfoF.td
[RISCV] Use frmarg instead of ixlenimm in PseudoFROUND. NFC (#171563)
2025-12-09 22:05:44 -08:00
RISCVInstrInfoM.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoP.td
[llvm][RISCV] Support mulh for P extension codegen (#171581)
2025-12-15 22:55:26 +08:00
RISCVInstrInfoQ.td
…
RISCVInstrInfoSFB.td
[RISCV] Add short forward branch support for lb, lbu, lh, lhu, lw, lwu and ld (#170829)
2025-12-17 08:57:20 +05:30
RISCVInstrInfoV.td
[RISCV] Add an OperandType to VMaskOp. NFC (#171926)
2025-12-11 20:03:47 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use VMV0 instead of VMaskOp in masked vector pseudoinstructions. NFC (#171924)
2025-12-11 20:02:50 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV][llvm] Support fminimum, fmaximum, fminnum, fmaxnum, fminimumnum, fmaximumnum codegen for zvfbfa (#171794)
2025-12-18 14:12:04 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV][llvm] Support fminimum, fmaximum, fminnum, fmaxnum, fminimumnum, fmaximumnum codegen for zvfbfa (#171794)
2025-12-18 14:12:04 +08:00
RISCVInstrInfoXAndes.td
[RISCV] Implement Clang Builtins for XAndesPerf Extension (#147018)
2025-12-17 08:43:37 +00:00
RISCVInstrInfoXCV.td
[RISCV] Use OPERAND_MEMORY as the OperandType for CVrr. NFC (#171967)
2025-12-11 22:02:48 -08:00
RISCVInstrInfoXMips.td
[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122)
2025-10-06 11:33:20 -07:00
RISCVInstrInfoXqccmp.td
…
RISCVInstrInfoXqci.td
[RISC-V] Add schedule information for Qualcomm extensions (#172601)
2025-12-18 14:25:53 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)
2025-12-10 17:46:10 -08:00
RISCVInstrInfoXSf.td
[RISCV] Add OperandType to tsimm5 used by Xsfvcp. (#171964)
2025-12-11 22:02:08 -08:00
RISCVInstrInfoXSfmm.td
[RISCV] Use vec_rm for VPseudoSF_MatMul_FRM. (#171573)
2025-12-10 13:14:46 -08:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
2025-08-21 13:12:46 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312)
2025-11-04 09:56:59 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrInfoZa.td
[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411)
2025-10-07 22:24:52 -07:00
RISCVInstrInfoZalasr.td
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
2025-10-07 21:30:09 -07:00
RISCVInstrInfoZb.td
[RISCV] Enable the zext.h alias for PACK with P. (#172756)
2025-12-17 19:49:30 -08:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZfa.td
…
RISCVInstrInfoZfbfmin.td
[RISCV] Add isel for bitcasting between bfloat and half types (#158828)
2025-09-17 12:10:47 -07:00
RISCVInstrInfoZfh.td
[RISCV] Enable rematerialization for scalar loads (#166774)
2025-11-24 18:14:19 +08:00
RISCVInstrInfoZibi.td
[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858)
2025-09-18 11:03:48 +08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZicfiss.td
[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483)
2025-09-15 00:57:31 +03:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVInstrInfoZimop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
[NFC][RISCV] Unify all zvfbfa vl patterns and sd node patterns (#171072)
2025-12-11 15:58:06 +08:00
RISCVInstrInfoZvfofp8min.td
[RISCV] Implement MC support for Zvfofp8min extension (#157014)
2025-09-19 07:49:31 +00:00
RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Remove outdated comment in RISCVInstrInfoZvqdotq.td.
2025-12-17 09:26:06 +08:00
RISCVInstrPredicates.td
[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well (#172111)
2025-12-16 22:32:20 +00:00
RISCVInterleavedAccess.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Rename -enable-p-ext-codegen -riscv-enable-p-ext-simd-codegen. (#172790)
2025-12-18 07:11:16 -08:00
RISCVISelDAGToDAG.h
[RISCV] Support XSfmm LLVM IR and CodeGen (#143069)
2025-10-14 02:01:57 +00:00
RISCVISelLowering.cpp
[RISCV][llvm] Remove custom legalization of fixed-length vector SPLAT_VECTOR (#172870)
2025-12-19 11:45:10 +08:00
RISCVISelLowering.h
[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)
2025-12-09 14:01:54 +08:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
[RISCV] Generate Xqcilsm QC_SETWMI store multiple instruction (#172438)
2025-12-16 22:12:26 +05:30
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781)
2025-10-03 08:53:58 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Refactor some code in RISCVMergeBaseOffset.NFC (#170839)
2025-12-06 07:38:46 +05:30
RISCVMoveMerger.cpp
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467)
2025-08-20 09:07:58 -07:00
RISCVOptWInstrs.cpp
[RISCV] Support P extension ABSW instruction. (#165047)
2025-10-30 08:42:38 -07:00
RISCVPassRegistry.def
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Rename SFB Base Feature (#169607)
2025-12-01 09:18:02 -08:00
RISCVProfiles.td
…
RISCVPromoteConstant.cpp
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV] Don't add duplicate Zilsd hints. (#169554)
2025-11-25 21:15:00 -08:00
RISCVRegisterInfo.h
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVRegisterInfo.td
[RISCV] Add fractional LMUL register classes for inline assembly. (#171278)
2025-12-09 20:59:33 -08:00
RISCVSchedAndes45.td
[RISCV] Fix typo in comment Interger->Integer. NFC
2025-08-13 11:19:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)
2025-12-10 13:59:13 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVSchedule.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVScheduleV.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVScheduleXSf.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125)
2025-11-16 18:26:03 +03:00
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[RISCV] Rename -enable-p-ext-codegen -riscv-enable-p-ext-simd-codegen. (#172790)
2025-12-18 07:11:16 -08:00
RISCVSubtarget.h
[RISCV] Rename -enable-p-ext-codegen -riscv-enable-p-ext-simd-codegen. (#172790)
2025-12-18 07:11:16 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Rename -enable-p-ext-codegen -riscv-enable-p-ext-simd-codegen. (#172790)
2025-12-18 07:11:16 -08:00
RISCVTargetTransformInfo.h
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl (#169885)
2025-12-04 01:34:29 +00:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
[RISCV] Commute Src in foldVMV_V_V (#170536)
2025-12-04 14:39:23 +08:00
RISCVVLOptimizer.cpp
[RISCV] Only reduce VLs of instructions with demanded VLs (#168693)
2025-11-20 03:49:59 +00:00
RISCVVMV0Elimination.cpp
…
RISCVZacasABIFix.cpp
…
RISCVZilsdOptimizer.cpp
[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182)
2025-11-22 23:16:31 -08:00