4877c593a8
Tasks completed: - Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to `faceforward(p1, p2, p3)` - Add pattern matching tests to `prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll` - Add CL extension error test `llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll` - Add CL extension test for no pattern matching in `llvm/test/CodeGen/SPIRV/opencl/faceforward.ll` Closes #137255.
212 lines
8.3 KiB
C++
212 lines
8.3 KiB
C++
//===-- SPIRVCombinerHelper.cpp -------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVCombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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using namespace MIPatternMatch;
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SPIRVCombinerHelper::SPIRVCombinerHelper(
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GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize,
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GISelValueTracking *VT, MachineDominatorTree *MDT, const LegalizerInfo *LI,
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const SPIRVSubtarget &STI)
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: CombinerHelper(Observer, B, IsPreLegalize, VT, MDT, LI), STI(STI) {}
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/// This match is part of a combine that
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/// rewrites length(X - Y) to distance(X, Y)
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/// (f32 (g_intrinsic length
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/// (g_fsub (vXf32 X) (vXf32 Y))))
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/// ->
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/// (f32 (g_intrinsic distance
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/// (vXf32 X) (vXf32 Y)))
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///
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bool SPIRVCombinerHelper::matchLengthToDistance(MachineInstr &MI) const {
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if (MI.getOpcode() != TargetOpcode::G_INTRINSIC ||
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cast<GIntrinsic>(MI).getIntrinsicID() != Intrinsic::spv_length)
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return false;
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// First operand of MI is `G_INTRINSIC` so start at operand 2.
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Register SubReg = MI.getOperand(2).getReg();
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MachineInstr *SubInstr = MRI.getVRegDef(SubReg);
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if (SubInstr->getOpcode() != TargetOpcode::G_FSUB)
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return false;
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return true;
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}
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void SPIRVCombinerHelper::applySPIRVDistance(MachineInstr &MI) const {
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// Extract the operands for X and Y from the match criteria.
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Register SubDestReg = MI.getOperand(2).getReg();
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MachineInstr *SubInstr = MRI.getVRegDef(SubDestReg);
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Register SubOperand1 = SubInstr->getOperand(1).getReg();
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Register SubOperand2 = SubInstr->getOperand(2).getReg();
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Register ResultReg = MI.getOperand(0).getReg();
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Builder.setInstrAndDebugLoc(MI);
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Builder.buildIntrinsic(Intrinsic::spv_distance, ResultReg)
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.addUse(SubOperand1)
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.addUse(SubOperand2);
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MI.eraseFromParent();
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}
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/// This match is part of a combine that
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/// rewrites select(fcmp(dot(I, Ng), 0), N, -N) to faceforward(N, I, Ng)
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/// (vXf32 (g_select
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/// (g_fcmp
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/// (g_intrinsic dot(vXf32 I) (vXf32 Ng)
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/// 0)
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/// (vXf32 N)
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/// (vXf32 g_fneg (vXf32 N))))
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/// ->
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/// (vXf32 (g_intrinsic faceforward
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/// (vXf32 N) (vXf32 I) (vXf32 Ng)))
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///
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/// This only works for Vulkan shader targets.
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///
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bool SPIRVCombinerHelper::matchSelectToFaceForward(MachineInstr &MI) const {
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if (!STI.isShader())
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return false;
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// Match overall select pattern.
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Register CondReg, TrueReg, FalseReg;
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if (!mi_match(MI.getOperand(0).getReg(), MRI,
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m_GISelect(m_Reg(CondReg), m_Reg(TrueReg), m_Reg(FalseReg))))
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return false;
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// Match the FCMP condition.
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Register DotReg, CondZeroReg;
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CmpInst::Predicate Pred;
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if (!mi_match(CondReg, MRI,
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m_GFCmp(m_Pred(Pred), m_Reg(DotReg), m_Reg(CondZeroReg))) ||
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!(Pred == CmpInst::FCMP_OLT || Pred == CmpInst::FCMP_ULT)) {
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if (!(Pred == CmpInst::FCMP_OGT || Pred == CmpInst::FCMP_UGT))
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return false;
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std::swap(DotReg, CondZeroReg);
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}
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// Check if FCMP is a comparison between a dot product and 0.
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MachineInstr *DotInstr = MRI.getVRegDef(DotReg);
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if (DotInstr->getOpcode() != TargetOpcode::G_INTRINSIC ||
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cast<GIntrinsic>(DotInstr)->getIntrinsicID() != Intrinsic::spv_fdot) {
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Register DotOperand1, DotOperand2;
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// Check for scalar dot product.
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if (!mi_match(DotReg, MRI,
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m_GFMul(m_Reg(DotOperand1), m_Reg(DotOperand2))) ||
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!MRI.getType(DotOperand1).isScalar() ||
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!MRI.getType(DotOperand2).isScalar())
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return false;
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}
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const ConstantFP *ZeroVal;
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if (!mi_match(CondZeroReg, MRI, m_GFCst(ZeroVal)) || !ZeroVal->isZero())
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return false;
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// Check if select's false operand is the negation of the true operand.
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auto AreNegatedConstantsOrSplats = [&](Register TrueReg, Register FalseReg) {
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std::optional<FPValueAndVReg> TrueVal, FalseVal;
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if (!mi_match(TrueReg, MRI, m_GFCstOrSplat(TrueVal)) ||
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!mi_match(FalseReg, MRI, m_GFCstOrSplat(FalseVal)))
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return false;
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APFloat TrueValNegated = TrueVal->Value;
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TrueValNegated.changeSign();
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return FalseVal->Value.compare(TrueValNegated) == APFloat::cmpEqual;
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};
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if (!mi_match(TrueReg, MRI, m_GFNeg(m_SpecificReg(FalseReg))) &&
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!mi_match(FalseReg, MRI, m_GFNeg(m_SpecificReg(TrueReg)))) {
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std::optional<FPValueAndVReg> MulConstant;
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MachineInstr *TrueInstr = MRI.getVRegDef(TrueReg);
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MachineInstr *FalseInstr = MRI.getVRegDef(FalseReg);
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if (TrueInstr->getOpcode() == TargetOpcode::G_BUILD_VECTOR &&
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FalseInstr->getOpcode() == TargetOpcode::G_BUILD_VECTOR &&
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TrueInstr->getNumOperands() == FalseInstr->getNumOperands()) {
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for (unsigned I = 1; I < TrueInstr->getNumOperands(); ++I)
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if (!AreNegatedConstantsOrSplats(TrueInstr->getOperand(I).getReg(),
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FalseInstr->getOperand(I).getReg()))
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return false;
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} else if (mi_match(TrueReg, MRI,
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m_GFMul(m_SpecificReg(FalseReg),
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m_GFCstOrSplat(MulConstant))) ||
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mi_match(FalseReg, MRI,
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m_GFMul(m_SpecificReg(TrueReg),
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m_GFCstOrSplat(MulConstant))) ||
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mi_match(TrueReg, MRI,
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m_GFMul(m_GFCstOrSplat(MulConstant),
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m_SpecificReg(FalseReg))) ||
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mi_match(FalseReg, MRI,
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m_GFMul(m_GFCstOrSplat(MulConstant),
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m_SpecificReg(TrueReg)))) {
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if (!MulConstant || !MulConstant->Value.isExactlyValue(-1.0))
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return false;
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} else if (!AreNegatedConstantsOrSplats(TrueReg, FalseReg))
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return false;
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}
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return true;
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}
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void SPIRVCombinerHelper::applySPIRVFaceForward(MachineInstr &MI) const {
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// Extract the operands for N, I, and Ng from the match criteria.
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Register CondReg = MI.getOperand(1).getReg();
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MachineInstr *CondInstr = MRI.getVRegDef(CondReg);
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Register DotReg = CondInstr->getOperand(2).getReg();
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CmpInst::Predicate Pred = cast<GFCmp>(CondInstr)->getCond();
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if (Pred == CmpInst::FCMP_OGT || Pred == CmpInst::FCMP_UGT)
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DotReg = CondInstr->getOperand(3).getReg();
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MachineInstr *DotInstr = MRI.getVRegDef(DotReg);
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Register DotOperand1, DotOperand2;
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if (DotInstr->getOpcode() == TargetOpcode::G_FMUL) {
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DotOperand1 = DotInstr->getOperand(1).getReg();
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DotOperand2 = DotInstr->getOperand(2).getReg();
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} else {
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DotOperand1 = DotInstr->getOperand(2).getReg();
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DotOperand2 = DotInstr->getOperand(3).getReg();
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}
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Register TrueReg = MI.getOperand(2).getReg();
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Register FalseReg = MI.getOperand(3).getReg();
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MachineInstr *TrueInstr = MRI.getVRegDef(TrueReg);
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if (TrueInstr->getOpcode() == TargetOpcode::G_FNEG ||
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TrueInstr->getOpcode() == TargetOpcode::G_FMUL)
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std::swap(TrueReg, FalseReg);
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MachineInstr *FalseInstr = MRI.getVRegDef(FalseReg);
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Register ResultReg = MI.getOperand(0).getReg();
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Builder.setInstrAndDebugLoc(MI);
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Builder.buildIntrinsic(Intrinsic::spv_faceforward, ResultReg)
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.addUse(TrueReg) // N
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.addUse(DotOperand1) // I
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.addUse(DotOperand2); // Ng
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SPIRVGlobalRegistry *GR =
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MI.getMF()->getSubtarget<SPIRVSubtarget>().getSPIRVGlobalRegistry();
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auto RemoveAllUses = [&](Register Reg) {
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SmallVector<MachineInstr *, 4> UsesToErase;
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for (auto &UseMI : MRI.use_instructions(Reg))
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UsesToErase.push_back(&UseMI);
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// calling eraseFromParent to early invalidates the iterator.
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for (auto *MIToErase : UsesToErase)
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MIToErase->eraseFromParent();
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};
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RemoveAllUses(CondReg); // remove all uses of FCMP Result
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GR->invalidateMachineInstr(CondInstr);
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CondInstr->eraseFromParent(); // remove FCMP instruction
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RemoveAllUses(DotReg); // remove all uses of spv_fdot/G_FMUL Result
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GR->invalidateMachineInstr(DotInstr);
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DotInstr->eraseFromParent(); // remove spv_fdot/G_FMUL instruction
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RemoveAllUses(FalseReg);
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GR->invalidateMachineInstr(FalseInstr);
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FalseInstr->eraseFromParent();
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}
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