ccedf259fc
conversion of bl memmove call to milicode bl .___memmove64[PR] in
64--bit mode is broken , the patch fix the problem.
in the llvm/include/llvm/IR/RuntimeLibcalls.td, we do not need to define
the
`def ___memmove64 : RuntimeLibcallImpl<MEMCPY>` in PPC64AIXCallList
` def ___memmove32 : RuntimeLibcallImpl<MEMCPY>` in PPC32AIXCallList
since there is function
```
/// Return a function impl compatible with RTLIB::MEMCPY, or
/// RTLIB::Unsupported if fully unsupported.
RTLIB::LibcallImpl getMemcpyImpl() const {
RTLIB::LibcallImpl Memcpy = getLibcallImpl(RTLIB::MEMCPY);
if (Memcpy == RTLIB::Unsupported) {
// Fallback to memmove if memcpy isn't available.
return getLibcallImpl(RTLIB::MEMMOVE);
}
return Memcpy;
}
```
182 lines
6.8 KiB
LLVM
182 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-LE-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-ibm-aix < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-AIX-64-P9
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define noundef i32 @_Z11memcmp_testPKvS0_m(ptr noundef readonly captures(none) %ptr1, ptr noundef readonly captures(none) %ptr2, i64 noundef %num) nounwind {
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; CHECK-LE-P9-LABEL: _Z11memcmp_testPKvS0_m:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: mflr r0
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; CHECK-LE-P9-NEXT: stdu r1, -32(r1)
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; CHECK-LE-P9-NEXT: std r0, 48(r1)
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; CHECK-LE-P9-NEXT: bl memcmp
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; CHECK-LE-P9-NEXT: nop
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; CHECK-LE-P9-NEXT: addi r1, r1, 32
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; CHECK-LE-P9-NEXT: ld r0, 16(r1)
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; CHECK-LE-P9-NEXT: mtlr r0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: _Z11memcmp_testPKvS0_m:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: mflr r0
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; CHECK-BE-P9-NEXT: stdu r1, -112(r1)
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; CHECK-BE-P9-NEXT: std r0, 128(r1)
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; CHECK-BE-P9-NEXT: bl memcmp
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; CHECK-BE-P9-NEXT: nop
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; CHECK-BE-P9-NEXT: addi r1, r1, 112
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; CHECK-BE-P9-NEXT: ld r0, 16(r1)
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; CHECK-BE-P9-NEXT: mtlr r0
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; CHECK-BE-P9-NEXT: blr
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;
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; CHECK-AIX-64-P9-LABEL: _Z11memcmp_testPKvS0_m:
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; CHECK-AIX-64-P9: # %bb.0: # %entry
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; CHECK-AIX-64-P9-NEXT: mflr r0
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; CHECK-AIX-64-P9-NEXT: stdu r1, -112(r1)
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; CHECK-AIX-64-P9-NEXT: std r0, 128(r1)
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; CHECK-AIX-64-P9-NEXT: bl .___memcmp64[PR]
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; CHECK-AIX-64-P9-NEXT: nop
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; CHECK-AIX-64-P9-NEXT: addi r1, r1, 112
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; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1)
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; CHECK-AIX-64-P9-NEXT: mtlr r0
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; CHECK-AIX-64-P9-NEXT: blr
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entry:
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%call = tail call i32 @memcmp(ptr noundef %ptr1, ptr noundef %ptr2, i64 noundef %num)
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ret i32 %call
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}
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declare i32 @memcmp(ptr noundef captures(none), ptr noundef captures(none), i64 noundef) nounwind
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define i64 @strlen_test(ptr noundef %str) nounwind {
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; CHECK-LE-P9-LABEL: strlen_test:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: mflr r0
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; CHECK-LE-P9-NEXT: stdu r1, -48(r1)
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; CHECK-LE-P9-NEXT: std r0, 64(r1)
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; CHECK-LE-P9-NEXT: std r3, 40(r1)
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; CHECK-LE-P9-NEXT: bl strlen
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; CHECK-LE-P9-NEXT: nop
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; CHECK-LE-P9-NEXT: addi r1, r1, 48
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; CHECK-LE-P9-NEXT: ld r0, 16(r1)
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; CHECK-LE-P9-NEXT: mtlr r0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: strlen_test:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: mflr r0
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; CHECK-BE-P9-NEXT: stdu r1, -128(r1)
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; CHECK-BE-P9-NEXT: std r0, 144(r1)
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; CHECK-BE-P9-NEXT: std r3, 120(r1)
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; CHECK-BE-P9-NEXT: bl strlen
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; CHECK-BE-P9-NEXT: nop
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; CHECK-BE-P9-NEXT: addi r1, r1, 128
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; CHECK-BE-P9-NEXT: ld r0, 16(r1)
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; CHECK-BE-P9-NEXT: mtlr r0
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; CHECK-BE-P9-NEXT: blr
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;
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; CHECK-AIX-64-P9-LABEL: strlen_test:
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; CHECK-AIX-64-P9: # %bb.0: # %entry
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; CHECK-AIX-64-P9-NEXT: mflr r0
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; CHECK-AIX-64-P9-NEXT: stdu r1, -128(r1)
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; CHECK-AIX-64-P9-NEXT: std r0, 144(r1)
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; CHECK-AIX-64-P9-NEXT: std r3, 120(r1)
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; CHECK-AIX-64-P9-NEXT: bl .___strlen64[PR]
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; CHECK-AIX-64-P9-NEXT: nop
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; CHECK-AIX-64-P9-NEXT: addi r1, r1, 128
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; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1)
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; CHECK-AIX-64-P9-NEXT: mtlr r0
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; CHECK-AIX-64-P9-NEXT: blr
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entry:
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%str.addr = alloca ptr, align 8
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store ptr %str, ptr %str.addr, align 8
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%0 = load ptr, ptr %str.addr, align 8
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%call = call i64 @strlen(ptr noundef %0)
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ret i64 %call
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}
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declare i64 @strlen(ptr noundef) nounwind
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define ptr @test_memmove(ptr noundef %destination, ptr noundef %source, i64 noundef %num) #0 {
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; CHECK-LE-P9-LABEL: test_memmove:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: mflr r0
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; CHECK-LE-P9-NEXT: .cfi_def_cfa_offset 80
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; CHECK-LE-P9-NEXT: .cfi_offset lr, 16
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; CHECK-LE-P9-NEXT: .cfi_offset r30, -16
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; CHECK-LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-LE-P9-NEXT: stdu r1, -80(r1)
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; CHECK-LE-P9-NEXT: std r0, 96(r1)
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; CHECK-LE-P9-NEXT: mr r30, r3
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; CHECK-LE-P9-NEXT: std r3, 56(r1)
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; CHECK-LE-P9-NEXT: std r4, 48(r1)
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; CHECK-LE-P9-NEXT: std r5, 40(r1)
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; CHECK-LE-P9-NEXT: bl memmove
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; CHECK-LE-P9-NEXT: nop
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; CHECK-LE-P9-NEXT: mr r3, r30
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; CHECK-LE-P9-NEXT: addi r1, r1, 80
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; CHECK-LE-P9-NEXT: ld r0, 16(r1)
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; CHECK-LE-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-LE-P9-NEXT: mtlr r0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test_memmove:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: mflr r0
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; CHECK-BE-P9-NEXT: stdu r1, -160(r1)
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; CHECK-BE-P9-NEXT: std r0, 176(r1)
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; CHECK-BE-P9-NEXT: .cfi_def_cfa_offset 160
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; CHECK-BE-P9-NEXT: .cfi_offset lr, 16
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; CHECK-BE-P9-NEXT: .cfi_offset r30, -16
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; CHECK-BE-P9-NEXT: std r30, 144(r1) # 8-byte Folded Spill
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; CHECK-BE-P9-NEXT: mr r30, r3
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; CHECK-BE-P9-NEXT: std r3, 136(r1)
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; CHECK-BE-P9-NEXT: std r4, 128(r1)
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; CHECK-BE-P9-NEXT: std r5, 120(r1)
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; CHECK-BE-P9-NEXT: bl memmove
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; CHECK-BE-P9-NEXT: nop
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; CHECK-BE-P9-NEXT: mr r3, r30
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; CHECK-BE-P9-NEXT: ld r30, 144(r1) # 8-byte Folded Reload
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; CHECK-BE-P9-NEXT: addi r1, r1, 160
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; CHECK-BE-P9-NEXT: ld r0, 16(r1)
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; CHECK-BE-P9-NEXT: mtlr r0
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; CHECK-BE-P9-NEXT: blr
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;
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; CHECK-AIX-64-P9-LABEL: test_memmove:
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; CHECK-AIX-64-P9: # %bb.0: # %entry
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; CHECK-AIX-64-P9-NEXT: mflr r0
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; CHECK-AIX-64-P9-NEXT: stdu r1, -144(r1)
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; CHECK-AIX-64-P9-NEXT: std r0, 160(r1)
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; CHECK-AIX-64-P9-NEXT: std r31, 136(r1) # 8-byte Folded Spill
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; CHECK-AIX-64-P9-NEXT: mr r31, r3
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; CHECK-AIX-64-P9-NEXT: std r3, 128(r1)
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; CHECK-AIX-64-P9-NEXT: std r4, 120(r1)
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; CHECK-AIX-64-P9-NEXT: std r5, 112(r1)
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; CHECK-AIX-64-P9-NEXT: bl .___memmove64[PR]
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; CHECK-AIX-64-P9-NEXT: nop
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; CHECK-AIX-64-P9-NEXT: mr r3, r31
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; CHECK-AIX-64-P9-NEXT: ld r31, 136(r1) # 8-byte Folded Reload
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; CHECK-AIX-64-P9-NEXT: addi r1, r1, 144
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; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1)
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; CHECK-AIX-64-P9-NEXT: mtlr r0
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; CHECK-AIX-64-P9-NEXT: blr
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entry:
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%destination.addr = alloca ptr, align 8
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%source.addr = alloca ptr, align 8
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%num.addr = alloca i64, align 8
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store ptr %destination, ptr %destination.addr, align 8
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store ptr %source, ptr %source.addr, align 8
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store i64 %num, ptr %num.addr, align 8
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%0 = load ptr, ptr %destination.addr, align 8
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%1 = load ptr, ptr %source.addr, align 8
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%2 = load i64, ptr %num.addr, align 8
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call void @llvm.memmove.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 %2, i1 false)
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ret ptr %0
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}
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declare void @llvm.memmove.p0.p0.i32(ptr writeonly captures(none), ptr readonly captures(none), i32, i1 immarg)
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