7486c6987e
Refines OpName emission to only target Global Variables, Functions, Function Parameters, Local Variables (allocas/phis), and Basic Blocks. This reduces binary size and clutter by avoiding OpName for every intermediate instruction (arithmetic, casts, etc.), while preserving readability for interfaces and program structure. Also updates the test suite to align with this change: - Removes OpName checks for intermediate instructions. - Adds side-effects (e.g., volatile stores) to tests where instructions were previously kept alive solely by their OpName usage. - Updates checks to use generic ID matching where specific names are no longer available. - Adds debug-info/opname-filtering.ll to verify the new policy.
27 lines
1.4 KiB
LLVM
27 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#int16:]] = OpTypeInt 16
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; CHECK-DAG: %[[#int32:]] = OpTypeInt 32
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; CHECK-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
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; CHECK-DAG: %[[#undef:]] = OpUndef %[[#int16_2]]
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; CHECK-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4{{$}}
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; CHECK-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8{{$}}
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; CHECK-NOT: %[[#idx1:]] = OpConstantNull %[[#int32]]
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; CHECK-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1{{$}}
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; CHECK: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
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; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
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; CHECK: %[[#res:]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v:]] %[[#index:]]
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define spir_kernel void @test(<2 x i16>* nocapture %out, i16 %v, i32 %index) {
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entry:
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%vec1 = insertelement <2 x i16> undef, i16 4, i32 0
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%vec2 = insertelement <2 x i16> %vec1, i16 8, i32 1
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%res = insertelement <2 x i16> %vec2, i16 %v, i32 %index
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store <2 x i16> %res, <2 x i16>* %out, align 4
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ret void
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}
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