Abhishek Varma b290a3e12b

[Linalg] Add *Pooling* matchers (#172351) ...

-- This commit is the eighth in the series of adding matchers
for linalg.*conv*/*pool*. Refer:
https://github.com/llvm/llvm-project/pull/163724
-- In this commit all variants of Pooling ops have been added.

Signed-off-by: Abhishek Varma <abhvarma@amd.com>

2025-12-19 13:01:02 +05:30

..

Affine

[mlir][affine] Use iter argument replace init when delete loop in the coalesceLoops function (#169514)

2025-12-01 10:00:54 +08:00

AMDGPU

[mlir][amdgpu] implement amdgpu.sparse_mfma wrapper for smfmac instructions (#171968)

2025-12-18 20:16:14 -06:00

AMX

[mlir][amx] Optional stride for tile load and store (#159569)

2025-10-13 14:22:44 +02:00

Arith

Add 'exact' flag to arith.shrui/shrsi/divsi/divui operations (#165923)

2025-11-17 09:46:39 -08:00

ArmNeon

[MLIR][AArch64] Lower vector.contract to Neon FEAT_BF16 operations (#148198)

2025-07-23 10:15:47 +01:00

ArmSME

[mlir][ArmSME] Remove ConvertIllegalShapeCastOpsToTransposes (#139706)

2025-06-25 16:40:14 +01:00

ArmSVE

[mlir][vector] Avoid setting padding by default to 0 in vector.transfer_read prefer ub.poison (#146088)

2025-06-30 15:20:42 -04:00

Async

[mlir][async]: Make async.execute operation with RecursiveMemoryEffects trait (#116544)

2025-07-31 16:42:10 +03:00

Bufferization

[mlir][bufferization] Enable moving dependent values in eliminate-empty-tensors (#169718)

2025-12-05 14:40:08 -05:00

Builtin

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Complex

[MLIR] Add new complex.powi op (#158722)

2025-09-19 01:36:13 +00:00

ControlFlow

[mlir][CF] Add ub.unreachable canonicalization (#169873)

2025-11-30 02:36:57 +00:00

DLTI

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EmitC

[mlir][emitc] Add address-of and dereference ops (#72569)

2025-12-03 12:41:29 +02:00

Func

[MLIR] Fix FileCheck annotations and add 32-bit coverage (#167149)

2025-11-09 00:39:08 +00:00

GPU

[mlir][gpu] Use arith dialect to lower gpu.global_id (#171614)

2025-12-13 18:43:12 +08:00

Index

[mlir] Add inliner interface to the index dialect (#170459)

2025-12-05 14:43:51 +00:00

IRDL

[MLIR][IRDL] Support camelCase segment size attributes in IRDL verifier (#168836)

2025-11-24 12:04:35 +08:00

Linalg

[Linalg] Add *Pooling* matchers (#172351)

2025-12-19 13:01:02 +05:30

LLVM

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LLVMIR

[mlir][rocdl] Add s_nop intrinsic (#172918)

2025-12-19 03:00:12 +03:00

Math

[MLIR][Vector] Remove vector.splat (#162167)

2025-10-10 09:58:18 -07:00

MemRef

[mlir] Clean up leftovers from moving linalg::Expand/CollapseShapeOp to memref dialect (#172448)

2025-12-16 12:14:45 +02:00

MLProgram

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MPI

[mlir][mpi] Mandatory Communicator (#133280)

2025-04-01 08:58:55 +02:00

NVGPU

[mlir][nvgpu] Add tma last dim bytes check (#153451)

2025-08-14 20:14:20 +08:00

OpenACC

[acc][test] add tests for RegionBranchOpInterface for acc regions (#172073)

2025-12-12 18:03:44 -05:00

OpenMP

[Flang][mlir] - Translation of delayed privatization for deferred target-tasks (#155348)

2025-10-22 12:18:56 -05:00

PDL

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PDLInterp

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Ptr

[mlir][ptr] Add ptr.ptr_diff operation (#157354)

2025-09-24 13:09:31 -04:00

Quant

Sub-channel quantized type implementation (#120172)

2025-03-23 07:37:55 -05:00

SCF

[MLIR][SCF] Verify number of regions in scf.reduce (#171450)

2025-12-11 12:39:39 +01:00

Shape

[mlir][bufferization][NFC] Rename to_memref to to_buffer (#137180)

2025-05-14 11:17:09 +02:00

Shard

[NFC][mlir][mesh,shard] Fixing misnomers in mesh dialect, renaming 'mesh' dialect to 'shard' (#150177)

2025-07-25 16:53:08 +02:00

SMT

[mlir][SMT] upstream SMT dialect (#131480)

2025-04-11 17:10:09 -04:00

SparseTensor

[mlir][SCF] Add scf.index_switch support for populateSCFStructuralTypeConversionsAndLegality (#160344)

2025-09-24 13:50:05 +02:00

SPIRV

[mlir][spirv] Add support for SwitchOp (#168713)

2025-11-20 15:19:10 +00:00

Tensor

[mlir][tensor] Fix bug in ConcatOpInterface (#168676)

2025-12-02 11:49:01 +08:00

Tosa

[mlir][tosa] Extend narrowing pass (#170712)

2025-12-16 10:11:13 +00:00

Transform

[MLIR][Transform] Return empty handles when the included sequence fails (#169782)

2025-11-28 19:17:58 +01:00

UB

[mlir][UB] Add ub.unreachable operation (#169872)

2025-11-28 10:35:18 +00:00

Vector

[MLIR][Vector] Add distribution pattern for vector::ConstantMaskOp (#172268)

2025-12-16 17:24:13 +01:00

WasmSSA

[MLIR][WASM] Control flow, conversion and comparison in Wasm importer (#154674)

2025-10-17 13:43:30 +02:00

X86Vector

[mlir][x86vector] Lower BF16 vector.contract to FMA using AVX2 BF16 packed ops. (#170267)

2025-12-17 14:41:58 +01:00

XeGPU

[MLIR][XeGPU] Fix the test issue brought by PR172125 (#172742)

2025-12-17 22:06:48 +00:00

common_folders.mlir

[MLIR] Allow constFoldBinaryOp to fold (T1, T1) -> T2 (#151410)

2025-08-07 17:52:03 +02:00

traits.mlir

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