34132754bd
instructions if they are conditional. Also fixed issues where the PC wasn't getting bit zero stripped for ARM targets when a stack frame was thumb. We now properly call through the GetOpcodeLoadAddress() functions to make sure the addresses are properly stripped for any targets that may decorate up their addresses. We now don't pass the SIGSTOP signals along. We can revisit this soon, but currently this was interfering with debugging some older ARM targets that don't have vCont support in the GDB server. llvm-svn: 134461
1000 lines
31 KiB
C++
1000 lines
31 KiB
C++
//===-- lldb_EmulateInstructionARM.h ------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_EmulateInstructionARM_h_
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#define lldb_EmulateInstructionARM_h_
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#include "lldb/Core/EmulateInstruction.h"
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#include "lldb/Core/Error.h"
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#include "lldb/Interpreter/NamedOptionValue.h"
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#include "Plugins/Process/Utility/ARMDefines.h"
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namespace lldb_private {
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// ITSession - Keep track of the IT Block progression.
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class ITSession
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{
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public:
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ITSession() : ITCounter(0), ITState(0) {}
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~ITSession() {}
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// InitIT - Initializes ITCounter/ITState.
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bool InitIT(uint32_t bits7_0);
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// ITAdvance - Updates ITCounter/ITState as IT Block progresses.
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void ITAdvance();
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// InITBlock - Returns true if we're inside an IT Block.
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bool InITBlock();
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// LastInITBlock - Returns true if we're the last instruction inside an IT Block.
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bool LastInITBlock();
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// GetCond - Gets condition bits for the current thumb instruction.
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uint32_t GetCond();
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private:
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uint32_t ITCounter; // Possible values: 0, 1, 2, 3, 4.
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uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially.
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};
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class EmulateInstructionARM : public EmulateInstruction
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{
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public:
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typedef enum
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{
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eEncodingA1,
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eEncodingA2,
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eEncodingA3,
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eEncodingA4,
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eEncodingA5,
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eEncodingT1,
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eEncodingT2,
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eEncodingT3,
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eEncodingT4,
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eEncodingT5
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} ARMEncoding;
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static void
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Initialize ();
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static void
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Terminate ();
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static const char *
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GetPluginNameStatic ();
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static const char *
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GetPluginDescriptionStatic ();
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static lldb_private::EmulateInstruction *
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CreateInstance (const lldb_private::ArchSpec &arch,
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InstructionType inst_type);
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static bool
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SupportsEmulatingIntructionsOfTypeStatic (InstructionType inst_type)
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{
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switch (inst_type)
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{
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case eInstructionTypeAny:
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case eInstructionTypePrologueEpilogue:
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case eInstructionTypePCModifying:
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return true;
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case eInstructionTypeAll:
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return false;
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default:
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break;
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}
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return false;
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}
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virtual const char *
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GetPluginName()
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{
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return "EmulateInstructionARM";
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}
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virtual const char *
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GetShortPluginName()
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{
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return GetPluginNameStatic();
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}
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virtual uint32_t
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GetPluginVersion()
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{
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return 1;
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}
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bool
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SetTargetTriple (const ArchSpec &arch);
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enum Mode
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{
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eModeInvalid = -1,
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eModeARM,
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eModeThumb
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};
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EmulateInstructionARM (const ArchSpec &arch) :
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EmulateInstruction (arch),
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m_arm_isa (0),
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m_opcode_mode (eModeInvalid),
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m_opcode_cpsr (0),
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m_it_session (),
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m_ignore_conditions (false)
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{
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SetArchitecture (arch);
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}
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// EmulateInstructionARM (const ArchSpec &arch,
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// bool ignore_conditions,
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// void *baton,
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// ReadMemory read_mem_callback,
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// WriteMemory write_mem_callback,
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// ReadRegister read_reg_callback,
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// WriteRegister write_reg_callback) :
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// EmulateInstruction (arch,
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// ignore_conditions,
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// baton,
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// read_mem_callback,
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// write_mem_callback,
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// read_reg_callback,
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// write_reg_callback),
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// m_arm_isa (0),
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// m_opcode_mode (eModeInvalid),
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// m_opcode_cpsr (0),
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// m_it_session ()
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// {
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// }
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virtual bool
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SupportsEmulatingIntructionsOfType (InstructionType inst_type)
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{
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return SupportsEmulatingIntructionsOfTypeStatic (inst_type);
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}
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virtual bool
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SetArchitecture (const ArchSpec &arch);
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virtual bool
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ReadInstruction ();
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virtual bool
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SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target);
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virtual bool
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EvaluateInstruction (uint32_t evaluate_options);
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virtual bool
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TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data);
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virtual bool
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GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info);
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virtual bool
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CreateFunctionEntryUnwind (UnwindPlan &unwind_plan);
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uint32_t
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ArchVersion();
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bool
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ConditionPassed (const uint32_t opcode,
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bool *is_conditional = NULL); // Filled in with true if the opcode is a conditional opcode
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// Filled in with false if the opcode is always executed
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uint32_t
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CurrentCond (const uint32_t opcode);
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// InITBlock - Returns true if we're in Thumb mode and inside an IT Block.
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bool InITBlock();
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// LastInITBlock - Returns true if we're in Thumb mode and the last instruction inside an IT Block.
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bool LastInITBlock();
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bool
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BadMode (uint32_t mode);
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bool
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CurrentModeIsPrivileged ();
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void
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CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate);
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bool
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BranchWritePC(const Context &context, uint32_t addr);
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bool
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BXWritePC(Context &context, uint32_t addr);
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bool
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LoadWritePC(Context &context, uint32_t addr);
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bool
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ALUWritePC(Context &context, uint32_t addr);
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Mode
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CurrentInstrSet();
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bool
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SelectInstrSet(Mode arm_or_thumb);
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bool
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WriteBits32Unknown (int n);
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bool
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WriteBits32UnknownToMemory (lldb::addr_t address);
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bool
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UnalignedSupport();
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typedef struct
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{
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uint32_t result;
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uint8_t carry_out;
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uint8_t overflow;
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} AddWithCarryResult;
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AddWithCarryResult
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AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in);
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// Helper method to read the content of an ARM core register.
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uint32_t
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ReadCoreReg (uint32_t regnum, bool *success);
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// See A8.6.96 MOV (immediate) Operation.
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// Default arguments are specified for carry and overflow parameters, which means
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// not to update the respective flags even if setflags is true.
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bool
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WriteCoreRegOptionalFlags (Context &context,
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const uint32_t result,
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const uint32_t Rd,
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bool setflags,
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const uint32_t carry = ~0u,
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const uint32_t overflow = ~0u);
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bool
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WriteCoreReg (Context &context,
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const uint32_t result,
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const uint32_t Rd)
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{
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// Don't set the flags.
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return WriteCoreRegOptionalFlags(context, result, Rd, false);
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}
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// See A8.6.35 CMP (immediate) Operation.
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// Default arguments are specified for carry and overflow parameters, which means
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// not to update the respective flags.
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bool
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WriteFlags (Context &context,
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const uint32_t result,
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const uint32_t carry = ~0u,
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const uint32_t overflow = ~0u);
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inline uint64_t
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MemARead (EmulateInstruction::Context &context,
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lldb::addr_t address,
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uint32_t size,
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uint64_t fail_value,
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bool *success_ptr)
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{
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// This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for
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// aligned reads from memory. Since we are not trying to write a full hardware simulator, and since
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// we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
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// system registers we would need in order to fully implement this function, we will just call
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// ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
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// the hardware, we can update this function appropriately.
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return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr);
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}
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inline bool
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MemAWrite (EmulateInstruction::Context &context,
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lldb::addr_t address,
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uint64_t data_val,
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uint32_t size)
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{
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// This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for
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// aligned writes to memory. Since we are not trying to write a full hardware simulator, and since
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// we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
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// system registers we would need in order to fully implement this function, we will just call
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// WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
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// the hardware, we can update this function appropriately.
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return WriteMemoryUnsigned (context, address, data_val, size);
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}
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inline uint64_t
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MemURead (EmulateInstruction::Context &context,
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lldb::addr_t address,
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uint32_t size,
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uint64_t fail_value,
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bool *success_ptr)
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{
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// This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for
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// unaligned reads from memory. Since we are not trying to write a full hardware simulator, and since
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// we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
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// system registers we would need in order to fully implement this function, we will just call
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// ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
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// the hardware, we can update this function appropriately.
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return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr);
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}
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inline bool
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MemUWrite (EmulateInstruction::Context &context,
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lldb::addr_t address,
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uint64_t data_val,
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uint32_t size)
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{
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// This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for
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// unaligned writes to memory. Since we are not trying to write a full hardware simulator, and since
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// we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
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// system registers we would need in order to fully implement this function, we will just call
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// WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
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// the hardware, we can update this function appropriately.
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return WriteMemoryUnsigned (context, address, data_val, size);
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}
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protected:
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// Typedef for the callback function used during the emulation.
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// Pass along (ARMEncoding)encoding as the callback data.
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typedef enum
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{
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eSize16,
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eSize32
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} ARMInstrSize;
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typedef struct
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{
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uint32_t mask;
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uint32_t value;
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uint32_t variants;
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EmulateInstructionARM::ARMEncoding encoding;
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uint32_t vfp_variants;
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ARMInstrSize size;
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bool (EmulateInstructionARM::*callback) (const uint32_t opcode, const EmulateInstructionARM::ARMEncoding encoding);
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const char *name;
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} ARMOpcode;
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uint32_t
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GetFramePointerRegisterNumber () const;
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uint32_t
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GetFramePointerDWARFRegisterNumber () const;
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static ARMOpcode*
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GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask);
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static ARMOpcode*
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GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask);
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// A8.6.123 PUSH
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bool
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EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.122 POP
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bool
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EmulatePOP (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.8 ADD (SP plus immediate)
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bool
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EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
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bool
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EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.97 MOV (register) -- move from r8-r15 to r0-r7
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bool
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EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.59 LDR (literal)
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bool
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EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.8 ADD (SP plus immediate)
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bool
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EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.9 ADD (SP plus register)
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bool
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EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.23 BL, BLX (immediate)
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bool
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EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.24 BLX (register)
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bool
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EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.25 BX
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bool
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EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.26 BXJ
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bool
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EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
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bool
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EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.215 SUB (SP minus immediate) -- Rd == ip
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bool
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EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.215 SUB (SP minus immediate)
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bool
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EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.216 SUB (SP minus register)
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bool
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EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.194 STR (immediate, ARM) -- Rn == sp
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bool
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EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.355 VPUSH
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bool
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EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.354 VPOP
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bool
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EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.218 SVC (previously SWI)
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bool
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EmulateSVC (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.50 IT
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bool
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EmulateIT (const uint32_t opcode, const ARMEncoding encoding);
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// NOP
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bool
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EmulateNop (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.16 B
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bool
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EmulateB (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.27 CBNZ, CBZ
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bool
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EmulateCB (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.226 TBB, TBH
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bool
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EmulateTB (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.4 ADD (immediate, Thumb)
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bool
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EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.5 ADD (immediate, ARM)
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bool
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EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.6 ADD (register)
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bool
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EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.7 ADD (register-shifted register)
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bool
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EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.97 MOV (register)
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bool
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EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.96 MOV (immediate)
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bool
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EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.35 CMP (immediate)
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bool
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EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.36 CMP (register)
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bool
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EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.14 ASR (immediate)
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bool
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EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.15 ASR (register)
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bool
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EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.88 LSL (immediate)
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bool
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EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.89 LSL (register)
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bool
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EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.90 LSR (immediate)
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bool
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EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.91 LSR (register)
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bool
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EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding);
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// A8.6.139 ROR (immediate)
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bool
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EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding);
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|
// A8.6.140 ROR (register)
|
|
bool
|
|
EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.141 RRX
|
|
bool
|
|
EmulateRRX (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// Helper method for ASR, LSL, LSR, ROR (immediate), and RRX
|
|
bool
|
|
EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
|
|
|
|
// Helper method for ASR, LSL, LSR, and ROR (register)
|
|
bool
|
|
EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
|
|
|
|
// LOAD FUNCTIONS
|
|
|
|
// A8.6.53 LDM/LDMIA/LDMFD
|
|
bool
|
|
EmulateLDM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.54 LDMDA/LDMFA
|
|
bool
|
|
EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.55 LDMDB/LDMEA
|
|
bool
|
|
EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.56 LDMIB/LDMED
|
|
bool
|
|
EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.57 LDR (immediate, Thumb) -- Encoding T1
|
|
bool
|
|
EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.58 LDR (immediate, ARM) - Encoding A1
|
|
bool
|
|
EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.59 LDR (literal)
|
|
bool
|
|
EmulateLDRLiteral (const uint32_t, const ARMEncoding encoding);
|
|
|
|
// A8.6.60 LDR (register) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3
|
|
bool
|
|
EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.62 LDRB (immediate, ARM)
|
|
bool
|
|
EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.63 LDRB (literal) - Encoding T1, A1
|
|
bool
|
|
EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.64 LDRB (register) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.65 LDRBT
|
|
bool
|
|
EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.66 LDRD (immediate)
|
|
bool
|
|
EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.67
|
|
bool
|
|
EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.68 LDRD (register)
|
|
bool
|
|
EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.69 LDREX
|
|
bool
|
|
EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.70 LDREXB
|
|
bool
|
|
EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.71 LDREXD
|
|
bool
|
|
EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.72 LDREXH
|
|
bool
|
|
EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3
|
|
bool
|
|
EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.74 LDRS (immediate, ARM)
|
|
bool
|
|
EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.75 LDRH (literal) - Encoding T1, A1
|
|
bool
|
|
EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.76 LDRH (register) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.77 LDRHT
|
|
bool
|
|
EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.79 LDRSB (literal) - Encoding T1, A1
|
|
bool
|
|
EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.80 LDRSB (register) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.81 LDRSBT
|
|
bool
|
|
EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.83 LDRSH (literal) - Encoding T1, A1
|
|
bool
|
|
EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.84 LDRSH (register) - Encoding T1, T2, A1
|
|
bool
|
|
EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.85 LDRSHT
|
|
bool
|
|
EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.86
|
|
bool
|
|
EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
|
|
// STORE FUNCTIONS
|
|
|
|
// A8.6.189 STM/STMIA/STMEA
|
|
bool
|
|
EmulateSTM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.190 STMDA/STMED
|
|
bool
|
|
EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.191 STMDB/STMFD
|
|
bool
|
|
EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.192 STMIB/STMFA
|
|
bool
|
|
EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.193 STR (immediate, Thumb)
|
|
bool
|
|
EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.194 STR (immediate, ARM)
|
|
bool
|
|
EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.195 STR (register)
|
|
bool
|
|
EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.196 STRB (immediate, Thumb)
|
|
bool
|
|
EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.197 STRB (immediate, ARM)
|
|
bool
|
|
EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.198 STRB (register)
|
|
bool
|
|
EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.199 STRBT
|
|
bool
|
|
EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.200 STRD (immediate)
|
|
bool
|
|
EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.201 STRD (register)
|
|
bool
|
|
EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.202 STREX
|
|
bool
|
|
EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.203 STREXB
|
|
bool
|
|
EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.204 STREXD
|
|
bool
|
|
EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.205 STREXH
|
|
bool
|
|
EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.206 STRH (immediate, Thumb)
|
|
bool
|
|
EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.207 STRH (immediate, ARM)
|
|
bool
|
|
EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.208 STRH (register)
|
|
bool
|
|
EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.209 STRHT
|
|
bool
|
|
EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.210 STRT
|
|
bool
|
|
EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.1 ADC (immediate)
|
|
bool
|
|
EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.2 ADC (Register)
|
|
bool
|
|
EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.10 ADR
|
|
bool
|
|
EmulateADR (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.11 AND (immediate)
|
|
bool
|
|
EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.12 AND (register)
|
|
bool
|
|
EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.19 BIC (immediate)
|
|
bool
|
|
EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.20 BIC (register)
|
|
bool
|
|
EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.26 BXJ
|
|
bool
|
|
EmulateBXJ (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.32 CMN (immediate)
|
|
bool
|
|
EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.33 CMN (register)
|
|
bool
|
|
EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.44 EOR (immediate)
|
|
bool
|
|
EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.45 EOR (register)
|
|
bool
|
|
EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.105 MUL
|
|
bool
|
|
EmulateMUL (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.106 MVN (immediate)
|
|
bool
|
|
EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.107 MVN (register)
|
|
bool
|
|
EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.113 ORR (immediate)
|
|
bool
|
|
EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.114 ORR (register)
|
|
bool
|
|
EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1
|
|
bool
|
|
EmulatePLDImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.119 PLI (immediate,literal) - Encoding T3, A1
|
|
bool
|
|
EmulatePLIImmediate (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.120 PLI (register) - Encoding T1, A1
|
|
bool
|
|
EmulatePLIRegister (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.141 RSB (immediate)
|
|
bool
|
|
EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.142 RSB (register)
|
|
bool
|
|
EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.144 RSC (immediate)
|
|
bool
|
|
EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.145 RSC (register)
|
|
bool
|
|
EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.150 SBC (immediate)
|
|
bool
|
|
EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.151 SBC (register)
|
|
bool
|
|
EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.211 SUB (immediate, Thumb)
|
|
bool
|
|
EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.212 SUB (immediate, ARM)
|
|
bool
|
|
EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.213 SUB (register)
|
|
bool
|
|
EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.214 SUB (register-shifted register)
|
|
bool
|
|
EmulateSUBRegShift (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.222 SXTB - Encoding T1
|
|
bool
|
|
EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.224 SXTH - EncodingT1
|
|
bool
|
|
EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.227 TEQ (immediate) - Encoding A1
|
|
bool
|
|
EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.228 TEQ (register) - Encoding A1
|
|
bool
|
|
EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.230 TST (immediate) - Encoding A1
|
|
bool
|
|
EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.231 TST (register) - Encoding T1, A1
|
|
bool
|
|
EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.262 UXTB - Encoding T1
|
|
bool
|
|
EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.264 UXTH - Encoding T1
|
|
bool
|
|
EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// B6.1.8 RFE
|
|
bool
|
|
EmulateRFE (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.319 VLDM
|
|
bool
|
|
EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.399 VSTM
|
|
bool
|
|
EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.307 VLD1 (multiple single elements)
|
|
bool
|
|
EmulateVLD1Multiple (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.308 VLD1 (single element to one lane)
|
|
bool
|
|
EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.309 VLD1 (single element to all lanes)
|
|
bool
|
|
EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.391 VST1 (multiple single elements)
|
|
bool
|
|
EmulateVST1Multiple (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.392 VST1 (single element from one lane)
|
|
bool
|
|
EmulateVST1Single (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// A8.6.317 VLDR
|
|
bool
|
|
EmulateVLDR (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
|
|
// A8.6.400 VSTR
|
|
bool
|
|
EmulateVSTR (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
// B6.2.13 SUBS PC, LR and related instructions
|
|
bool
|
|
EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding);
|
|
|
|
uint32_t m_arm_isa;
|
|
Mode m_opcode_mode;
|
|
uint32_t m_opcode_cpsr;
|
|
uint32_t m_new_inst_cpsr; // This can get updated by the opcode.
|
|
ITSession m_it_session;
|
|
bool m_ignore_conditions;
|
|
};
|
|
|
|
} // namespace lldb_private
|
|
|
|
#endif // lldb_EmulateInstructionARM_h_
|